公开(公告)号：US08853015B1

公开(公告)日：2014-10-07

申请号：US13863393

申请日：2013-04-16

Applicant: United Microelectronics Corp.

Inventor： Lung-En Kuo ,  Po-Wen Su ,  Chen-Yi Weng ,  Hsuan-Hsu Chen

IPC: H01L21/00 ,  H01L21/762 ,  H01L29/78

CPC classification number: H01L29/7851 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7853

Abstract: A method of forming a fin structure is provided. First, a substrate is provided, wherein a first region, a second region encompassing the first region, and a third region encompassing the second region are defined on the substrate. Then, a plurality of first trenches having a first depth are formed in the first region and the second region, wherein each two first trenches defines a first fin structure. The first fin structure in the second region is removed. Lastly, the first trenches are deepened to form a plurality of second trenches having a second depth, wherein each two second trenches define a second fin structure. The present invention further provides a structure of a non-planar transistor.

Abstract translation: 提供一种形成翅片结构的方法。 首先，提供衬底，其中第一区域，包围第一区域的第二区域和包围第二区域的第三区域被限定在衬底上。 然后，在第一区域和第二区域中形成具有第一深度的多个第一沟槽，其中每两个第一沟槽限定第一鳍结构。 第二区域中的第一鳍结构被去除。 最后，加深第一沟槽以形成具有第二深度的多个第二沟槽，其中每两个第二沟槽限定第二鳍结构。 本发明还提供了一种非平面晶体管的结构。

公开(公告)号：US20240339532A1

公开(公告)日：2024-10-10

申请号：US18743061

申请日：2024-06-13

Applicant: United Microelectronics Corp.

Inventor： Po-Wen Su ,  Ming-Hua Chang ,  Shui-Yen Lu

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7787

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a patterned mask on the buffer layer, using the patterned mask to remove the buffer layer for forming ridges and a damaged layer on the ridges; removing the damaged layer, forming a barrier layer on the ridges; and forming a p-type semiconductor layer on the barrier layer.

公开(公告)号：US20240322030A1

公开(公告)日：2024-09-26

申请号：US18732645

申请日：2024-06-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Wen Su ,  Ming-Hua Chang ,  Shui-Yen Lu

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7787

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, ridges extending along a first direction on the buffer layer, gaps extending along the first direction between the ridges, a p-type semiconductor layer extending along a second direction on the ridges and inserted into the gaps, and a source electrode and a drain electrode adjacent to two sides of the p-type semiconductor layer. Preferably, the source electrode and the drain electrode are extending along the second direction and directly on top of the ridges.

公开(公告)号：US11810786B2

公开(公告)日：2023-11-07

申请号：US17385969

申请日：2021-07-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Wen Su ,  Cheng-Han Lu

IPC: H01L21/027 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/033 ,  H01L21/311 ,  H01L21/308

CPC classification number: H01L21/0274 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/76892

Abstract: A method for fabricating a semiconductor device includes following steps: A patterned mask layer including a plurality of standing walls and a covering part is formed on a surface of a semiconductor substrate, wherein two adjacent standing walls define a first opening exposing a part of the surface, and the covering part blankets the surface. A first patterned photoresist layer is formed to partially cover the covering part. A first etching process is performed to form a first trench in the substrate, passing through the surface and aligning with the first opening. A portion of the patterned mask layer is removed to form a second opening exposing another portion of the surface. A second etching process is performed to form a second trench in the substrate and define an active area on the surface. The depth of the first trench is greater than that of the second trench.

公开(公告)号：US11552187B2

公开(公告)日：2023-01-10

申请号：US16809524

申请日：2020-03-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Wen Su ,  Ming-Hua Chang ,  Shui-Yen Lu

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/06 ,  H01L29/66 ,  H01L29/20

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a patterned mask on the buffer layer; using the patterned mask to remove the buffer layer for forming ridges and a damaged layer on the ridges; removing the damaged layer; forming a barrier layer on the ridges; and forming a p-type semiconductor layer on the barrier layer.

公开(公告)号：US20220077300A1

公开(公告)日：2022-03-10

申请号：US17524723

申请日：2021-11-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jie-Ning Yang ,  Wen-Tsung Chang ,  Po-Wen Su ,  Kuan-Ying Lai ,  Bo-Yu Su ,  Chun-Mao Chiou ,  Yao-Jhan Wang

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/417

Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

公开(公告)号：US11205705B2

公开(公告)日：2021-12-21

申请号：US16205174

申请日：2018-11-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jie-Ning Yang ,  Wen-Tsung Chang ,  Po-Wen Su ,  Kuan-Ying Lai ,  Bo-Yu Su ,  Chun-Mao Chiou ,  Yao-Jhan Wang

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/417

Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

公开(公告)号：US10522652B1

公开(公告)日：2019-12-31

申请号：US16129502

申请日：2018-09-12

Applicant: United Microelectronics Corp.

Inventor： Po-Wen Su ,  Chih-Wei Lin ,  Wei-Chih Lai ,  Tai-Yen Lin

IPC: H01L21/8234 ,  H01L21/3213 ,  H01L21/306 ,  H01L21/321 ,  H01L29/66 ,  H01L27/088 ,  H01L21/033 ,  H01L21/3105

Abstract: A semiconductor device and a method for fabricating the same are provided. A structure of the semiconductor device includes a substrate having a device region and an edge region. A plurality of device structures is formed on the substrate. An etching stop layer is disposed in the edge region of the substrate. The etching stop layer is converted from P-type dopants from an exposed surface layer of the substrate.

公开(公告)号：US10199260B1

公开(公告)日：2019-02-05

申请号：US15726358

申请日：2017-10-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Wen Su ,  Hsuan-Tai Hsu ,  Kuan-Hsuan Ku

IPC: H01L21/768 ,  H01L29/417 ,  H01L23/522 ,  H01L21/311

Abstract: A method of fabricating a contact hole structure includes providing a substrate with an epitaxial layer embedded therein. Next, an interlayer dielectric is formed to cover the substrate. After that, a first hole is formed in the interlayer dielectric and the epitaxial layer. Later, a mask layer is formed to cover a sidewall of the first hole and expose a bottom of the first hole. Subsequently, a second hole is formed by etching the epitaxial layer at the bottom of the first hole and taking the mask layer and the interlayer dielectric as a mask, wherein the first hole and the second hole form a contact hole. Then, the mask layer is removed. Finally, a silicide layer is formed to cover the contact hole.

公开(公告)号：US10043882B2

公开(公告)日：2018-08-07

申请号：US15863990

申请日：2018-01-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Wen Su ,  Zhen Wu ,  Hsiao-Pang Chou ,  Chiu-Hsien Yeh ,  Shui-Yen Lu ,  Jian-Wei Chen

IPC: H01L29/51 ,  H01L29/40 ,  H01L29/423 ,  H01L21/82 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

Abstract: A method of forming a semiconductor device includes the following steps. A substrate is provided, and the substrate has a first region. A barrier layer is then formed on the first region of the substrate. A first work function layer is formed on the barrier layer. An upper half portion of the first work function layer is converted into a non-volatile material layer. The non-volatile material layer is removed and a lower half portion of the first work function layer is kept.