公开(公告)号：US20170162389A1

公开(公告)日：2017-06-08

申请号：US15439890

申请日：2017-02-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuang-Hsiu Chen ,  Yi-Liang Ye ,  Chueh-Yang Liu ,  Yu-Ren Wang

IPC: H01L21/033 ,  H01L29/66 ,  H01L29/78 ,  H01L29/24 ,  H01L29/267 ,  H01L29/08 ,  H01L21/02 ,  H01L21/8238

CPC classification number: H01L21/0335 ,  H01L21/02521 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/26513 ,  H01L21/3105 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/24 ,  H01L29/267 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: A method for fabricating the semiconductor device is disclosed. A semiconductor substrate having a main surface is provided. A gate is formed on the main surface of the semiconductor substrate. An offset liner is formed on the sidewall of the gate. An ion implantation process is performed to form lightly doped drain (LDD) region in the semiconductor substrate. A spacer is formed on a sidewall of the gate. A cavity is recessed into the main surface of the semiconductor substrate. The cavity is adjacent to the spacer. An epitaxial layer is grown in the cavity. The spacer is then subjected to a surface treatment to form a dense oxide film on the spacer. A mask layer is deposited on the dense oxide film. The dense oxide film has a thickness that is smaller or equal to 12 angstroms.

公开(公告)号：US20160314969A1

公开(公告)日：2016-10-27

申请号：US15166291

申请日：2016-05-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Kuang-Hsiu Chen ,  Ted Ming-Lang Guo ,  Yu-Ren Wang

IPC: H01L21/02 ,  H01L21/76 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/306 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L21/02636 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/76 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/42356 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: The present invention provides a method for forming a semiconductor structure, comprising: firstly, a substrate is provided, next, a first dry etching process is performed, to form a recess in the substrate. Afterwards, an ion implantation process is performed to a bottom surface of the recess, a wet etching process is then performed, to etch partial sidewalls of the recess, so as to form at least two tips on two sides of the recess respectively, and a second dry etching process is performed, to etch partial bottom surface of the recess, wherein after the second dry etching process is performed, a lower portion of the recess has a U-shaped cross section profile.

Abstract translation: 本发明提供一种形成半导体结构的方法，包括：首先提供衬底，然后进行第一干蚀刻工艺，以在衬底中形成凹陷。 之后，对凹部的底面执行离子注入工艺，然后执行湿蚀刻工艺，以蚀刻凹部的部分侧壁，从而分别在凹槽的两侧形成至少两个尖端，并且 进行第二干蚀刻工艺，以蚀刻凹部的部分底表面，其中在执行第二干蚀刻工艺之后，凹部的下部具有U形横截面轮廓。

公开(公告)号：US09419089B1

公开(公告)日：2016-08-16

申请号：US14714361

申请日：2015-05-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Kuang-Hsiu Chen ,  Ted Ming-Lang Guo ,  Yu-Ren Wang

IPC: H01L29/06 ,  H01L29/423 ,  H01L21/3065 ,  H01L21/225 ,  H01L21/283

CPC classification number: H01L21/02636 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/76 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/42356 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: The present invention provides a semiconductor structure, which includes a substrate, at least two gate structures disposed on the substrate, a first recess, disposed in the substrate between two gate structures, the first recess having a U-shaped cross section profile, and a second recess, disposed on the first recess, the second recess having a polygonal shaped cross section profile, and has at least two tips on two sides of the second recess, the first recess and the second recess forming an epitaxial recess.

Abstract translation: 本发明提供了一种半导体结构，其包括基板，设置在基板上的至少两个栅极结构，设置在两个栅极结构之间的基板中的第一凹部，第一凹部具有U形横截面轮廓，以及 第二凹部，设置在第一凹部上，第二凹部具有多边形截面轮廓，并且在第二凹部的两侧具有至少两个尖端，第一凹部和第二凹部形成外延凹部。

公开(公告)号：US20250072060A1

公开(公告)日：2025-02-27

申请号：US18943871

申请日：2024-11-11

Applicant: United Microelectronics Corp.

Inventor： Kuang-Hsiu Chen ,  Wei-Chung Sun ,  Chao Nan Chen ,  Chun-Wei Yu ,  Kuan Hsuan Ku ,  Shao-Wei Wang

IPC: H01L29/66

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The manufacturing method of the semiconductor structure includes the following. A gate structure is formed on a substrate. A tilt implanting process is performed to implant group IV elements into the substrate to form a doped region, and the doped region is located on two sides of the gate structure and partially located under the gate structure. A part of the substrate on two sides of the gate structure is removed to form a first recess. A cleaning process is performed on the surface of the first recess. A wet etching process is performed on the first recess to form a second recess. A semiconductor layer is formed in the second recess.

公开(公告)号：US12021134B2

公开(公告)日：2024-06-25

申请号：US18073539

申请日：2022-12-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chih Chuang ,  Chia-Jong Liu ,  Kuang-Hsiu Chen ,  Chung-Ting Huang ,  Chi-Hsuan Tang ,  Kai-Hsiang Wang ,  Bing-Yang Jiang ,  Yu-Lin Cheng ,  Chun-Jen Chen ,  Yu-Shu Lin ,  Jhong-Yi Huang ,  Chao-Nan Chen ,  Guan-Ying Wu

IPC: H01L29/66 ,  H01L29/423

CPC classification number: H01L29/6656 ,  H01L29/42364

Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.

公开(公告)号：US20230097129A1

公开(公告)日：2023-03-30

申请号：US18073539

申请日：2022-12-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chih Chuang ,  Chia-Jong Liu ,  Kuang-Hsiu Chen ,  Chung-Ting Huang ,  Chi-Hsuan Tang ,  Kai-Hsiang Wang ,  Bing-Yang Jiang ,  Yu-Lin Cheng ,  Chun-Jen Chen ,  Yu-Shu Lin ,  Jhong-Yi Huang ,  Chao-Nan Chen ,  Guan-Ying Wu

IPC: H01L29/66 ,  H01L29/423

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer and a second spacer around the gate structure; forming a recess adjacent to two sides of the second spacer; performing a cleaning process to trim the second spacer for forming a void between the first spacer and the substrate; and forming an epitaxial layer in the recess.

公开(公告)号：US20210280717A1

公开(公告)日：2021-09-09

申请号：US17330443

申请日：2021-05-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuang-Hsiu Chen ,  Sung-Yuan Tsai ,  Chi-Hsuan Tang ,  Chun-Wei Yu ,  Yu-Ren Wang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/36 ,  H01L29/66 ,  H01L29/423

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure and an epitaxial structure. The gate structure is disposed on the substrate, and the epitaxial structure is disposed in the substrate, at one side of the gate structure. The epitaxial structure includes a portion being protruded from a top surface of the substrate, and the portion includes a discontinuous sidewall, with a distance between a turning point of the discontinuous sidewalls and the gate structure being a greatest distance between the epitaxial structure and the gate structure.

公开(公告)号：US20210151580A1

公开(公告)日：2021-05-20

申请号：US17160421

申请日：2021-01-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chih Chuang ,  Chia-Jong Liu ,  Kuang-Hsiu Chen ,  Chung-Ting Huang ,  Chi-Hsuan Tang ,  Kai-Hsiang Wang ,  Bing-Yang Jiang ,  Yu-Lin Cheng ,  Chun-Jen Chen ,  Yu-Shu Lin ,  Jhong-Yi Huang ,  Chao-Nan Chen ,  Guan-Ying Wu

IPC: H01L29/66 ,  H01L29/423

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer and a second spacer around the gate structure; forming a recess adjacent to two sides of the second spacer; performing a cleaning process to trim the second spacer for forming a void between the first spacer and the substrate; and forming an epitaxial layer in the recess.

公开(公告)号：US10943991B2

公开(公告)日：2021-03-09

申请号：US16294877

申请日：2019-03-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chih Chuang ,  Chia-Jong Liu ,  Kuang-Hsiu Chen ,  Chung-Ting Huang ,  Chi-Hsuan Tang ,  Kai-Hsiang Wang ,  Bing-Yang Jiang ,  Yu-Lin Cheng ,  Chun-Jen Chen ,  Yu-Shu Lin ,  Jhong-Yi Huang ,  Chao-Nan Chen ,  Guan-Ying Wu

IPC: H01L29/66 ,  H01L29/423

Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided, in which the method includes the steps of forming a gate structure on a substrate, forming a spacer on a sidewall of the gate structure, forming two recesses adjacent to two sides of the spacer, performing a cleaning process to trim the spacer for forming a void between the spacer and the substrate, and forming two portions of an epitaxial layer in the two recesses. The semiconductor device preferably includes a cap layer on the two portions of the epitaxial layer as the cap layer includes a planar top surface and an inclined sidewall.

公开(公告)号：US20200098916A1

公开(公告)日：2020-03-26

申请号：US16172856

申请日：2018-10-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuang-Hsiu Chen ,  Sung-Yuan Tsai ,  Chi-Hsuan Tang ,  Kai-Hsiang Wang ,  Chao-Nan Chen ,  Shi-You Liu ,  Chun-Wei Yu ,  Yu-Ren Wang

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L21/265

Abstract: A semiconductor device is disclosed. The semiconductor device comprises a substrate, a gate structure disposed on the substrate, a spacer disposed on the substrate and covering a sidewall of the gate structure, an air gap sandwiched between the spacer and the substrate, and a source/drain region disposed in the substrate and having a faceted surface exposed from the substrate, wherein the faceted surface borders the substrate on a boundary between the air gap and the substrate.