公开(公告)号：US20240088293A1

公开(公告)日：2024-03-14

申请号：US17960146

申请日：2022-10-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ya Chiu ,  Ssu-I Fu ,  Chin-Hung Chen ,  Jin-Yan Chiou ,  Wei-Chuan Tsai ,  Yu-Hsiang Lin

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66

CPC classification number: H01L29/7847 ,  H01L21/26506 ,  H01L21/324 ,  H01L29/665

Abstract: An n-type metal oxide semiconductor transistor includes a gate structure, two source/drain regions, two amorphous portions and a silicide. The gate structure is disposed on a substrate. The two source/drain regions are disposed in the substrate and respectively located at two sides of the gate structure, wherein at least one of the source/drain regions is formed with a dislocation. The two amorphous portions are respectively disposed in the two source/drain regions. The silicide is disposed on the two source/drain regions, wherein at least one portion of the silicide overlaps the two amorphous portions.

公开(公告)号：US20220122915A1

公开(公告)日：2022-04-21

申请号：US17073413

申请日：2020-10-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Tsai Yi ,  Wei-Chuan Tsai ,  Jin-Yan Chiou ,  Hsiang-Wen Ke

IPC: H01L23/535 ,  H01L23/522 ,  H01L23/532 ,  H01L21/321 ,  H01L21/768

Abstract: A semiconductor structure includes a substrate; a first inter-layer dielectric (ILD) layer on the substrate; an etch stop layer on the first ILD layer; a second inter-layer dielectric (ILD) layer on the etch stop layer; and a copper damascene interconnect layer disposed in the first ILD layer. A tungsten via structure is disposed in the second ILD layer and the etch stop layer, and is electrically connected to the copper damascene interconnect layer. The tungsten via structure includes a tungsten layer and a barrier layer surrounding the tungsten layer. An intermetallic layer is disposed between the barrier layer and the copper damascene interconnect layer.

公开(公告)号：US20190122925A1

公开(公告)日：2019-04-25

申请号：US16224818

申请日：2018-12-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Han Chen ,  Yen-Tsai Yi ,  Chun-Chieh Chiu ,  Min-Chuan Tsai ,  Wei-Chuan Tsai ,  Hsin-Fu Huang

IPC: H01L21/768 ,  H01L29/08 ,  H01L29/417 ,  H01L29/267 ,  H01L29/24 ,  H01L29/16 ,  H01L29/161 ,  H01L23/485 ,  H01L23/532 ,  H01L23/535 ,  H01L29/66

Abstract: A conductive structure includes a substrate including a first dielectric layer formed thereon, at least a first opening formed in the first dielectric layer, a low resistive layer formed in the opening, and a first metal bulk formed on the lower resistive layer in the opening. The first metal bulk directly contacts a surface of the first low resistive layer. The low resistive layer includes a carbonitride of a first metal material, and the first metal bulk includes the first metal material.

公开(公告)号：US20180151428A1

公开(公告)日：2018-05-31

申请号：US15361503

申请日：2016-11-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Han Chen ,  Yen-Tsai Yi ,  Chun-Chieh Chiu ,  Min-Chuan Tsai ,  Wei-Chuan Tsai ,  Hsin-Fu Huang

IPC: H01L21/768 ,  H01L23/535 ,  H01L23/532 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/78

CPC classification number: H01L21/76889 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/7848

Abstract: A conductive structure includes a substrate including a first dielectric layer formed thereon, at least a first opening formed in the first dielectric layer, a low resistive layer formed in the opening, and a first metal bulk formed on the lower resistive layer in the opening. The first metal bulk directly contacts a surface of the first low resistive layer. The low resistive layer includes a carbonitride of a first metal material, and the first metal bulk includes the first metal material.

公开(公告)号：US09887158B1

公开(公告)日：2018-02-06

申请号：US15340982

申请日：2016-11-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Kuo-Chin Hung ,  Min-Chuan Tsai ,  Wei-Chuan Tsai ,  Yi-Han Liao ,  Chun-Tsen Lu ,  Fu-Shou Tsai ,  Li-Chieh Hsu

IPC: H01L23/52 ,  H01L29/41 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L29/417 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/5228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/41758 ,  H01L29/66628 ,  H01L29/7833

Abstract: A conductive structure includes a substrate including a first dielectric layer formed thereon, a first trench formed in the first dielectric layer, a first barrier layer formed in the first trench, a first nucleation layer formed on the first barrier layer, a first metal layer formed on the first nucleation layer, and a first high resistive layer sandwiched in between the first barrier layer and the first metal layer.

公开(公告)号：US09853123B2

公开(公告)日：2017-12-26

申请号：US14924723

申请日：2015-10-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chin Hung ,  Wei-Chuan Tsai ,  Kuan-Chun Lin

IPC: H01L29/66 ,  H01L23/535 ,  H01L23/532 ,  H01L29/49 ,  H01L21/768

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659

Abstract: A semiconductor structure includes a substrate having thereon a dielectric layer. An opening is formed in the dielectric layer. The opening includes a bottom surface and a sidewall surface. A diffusion barrier layer is conformally disposed along the sidewall surface and the bottom surface of the opening. A nucleation metal layer is conformally disposed on the diffusion barrier layer. A bulk metal layer is disposed on the nucleation metal layer. A film-growth retarding layer is disposed between the nucleation metal layer and the bulk metal layer.

公开(公告)号：US20170117379A1

公开(公告)日：2017-04-27

申请号：US14924532

申请日：2015-10-27

Applicant: United Microelectronics Corp.

Inventor： Pin-Hong Chen ,  Kuo-Chih Lai ,  Chia-Chang Hsu ,  Chun-Chieh Chiu ,  Li-Han Chen ,  Min-Chuan Tsai ,  Kuo-Chin Hung ,  Wei-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu

IPC: H01L29/66 ,  H01L21/285 ,  H01L29/78

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L29/267 ,  H01L29/45 ,  H01L29/7845 ,  H01L29/785

Abstract: A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.