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    BIDIRECTIONAL INSULATED GATE BIPOLAR TRANSISTOR
    32.
    发明申请
    BIDIRECTIONAL INSULATED GATE BIPOLAR TRANSISTOR 有权
    双向绝缘门双极晶体管

    公开(公告)号：US20160322483A1

    公开(公告)日：2016-11-03

    申请号：US15209745

    申请日：2016-07-13

    Applicant: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA ,  INSTITUTE OF ELECTRONIC AND INFORMATION ENGINEERING IN DONGGUAN, UESTC

    Inventor： Jinping ZHANG ,  Yadong SHAN ,  Gaochao XU ,  Xin YAO ,  Jingxiu LIU ,  Zehong LI ,  Min REN ,  Bo ZHANG

    IPC: H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

    CPC classification number: H01L29/7397 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/4236

    Abstract: A bidirectional IGBT device, including a cellular structure including: two MOS structures, a substrate drift layer, two highly doped buried layers operating for carrier storage or field stop, two metal electrodes, and isolating dielectrics. Each MOS structure includes: a body region, a heavily doped source region, a body contact region, and a gate structure. Each gate structure includes: a gate dielectric and a gate conductive material. The two MOS structures are symmetrically disposed on the top surface and the back surface of the substrate drift layer. The heavily doped source region and the body contact region are disposed in the body region and independent from each other, and both surfaces of the heavily doped source region and the body contact region are connected to each of the two metal electrodes. The gate dielectric separates the gate conductive material from a channel region of each of the MOS structures.

    Abstract translation: 一种双向IGBT器件，其包括：两个MOS结构，衬底漂移层，用于载流子存储或场停止的两个高掺杂掩埋层，两个金属电极和隔离电介质。 每个MOS结构包括：体区，重掺杂源区，体接触区和栅结构。 每个栅极结构包括：栅极电介质和栅极导电材料。 两个MOS结构对称地设置在衬底漂移层的顶表面和背表面上。 重掺杂源极区域和体接触区域设置在体区域中并且彼此独立，并且重掺杂源极区域和体接触区域的两个表面连接到两个金属电极中的每一个。 栅极电介质将栅极导电材料与每​​个MOS结构的沟道区分离。

    LATERAL POWER SEMICONDUCTOR DEVICE LAYOUT AND DEVICE STRUCTURE
    33.
    发明申请
    LATERAL POWER SEMICONDUCTOR DEVICE LAYOUT AND DEVICE STRUCTURE 有权

    公开(公告)号：US20250107137A1

    公开(公告)日：2025-03-27

    申请号：US18398222

    申请日：2023-12-28

    Applicant: University of Electronic Science and Technology of China

    Inventor： Ming QIAO ,  Jiawei WANG ,  Dingxiang MA ,  Yue GAO ,  Gen LIU ,  Shengduo WANG ,  Yuanqing YE ,  Bo ZHANG

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417

    Abstract: A lateral power semiconductor device layout and a device structure belong to the technical field of power semiconductor devices. A method for designing a lateral power semiconductor device layout with high integrity and high cell density has the following advantages of reducing a specific on-resistance of the device, increasing a width of a channel per unit area, improving the current capability of the device, optimizing the static characteristic of the device, reducing the area of a drain region and the parasitic capacitance of the device, reducing the delay time of a cell switch caused by an excessively long gate electrode of a traditional finger cell, optimizing the dynamic characteristic of the device, optimizing the cell edge of the device and the curvature effect of a terminal, and reducing the pre-breakdown risk of the device.

    SHARED-APERTURE ANTENNA
    34.
    发明申请
    SHARED-APERTURE ANTENNA 审中-公开

    公开(公告)号：US20200076086A1

    公开(公告)日：2020-03-05

    申请号：US16556258

    申请日：2019-08-30

    Applicant: University of Electronic Science and Technology of China

    Inventor： Yujian CHENG ,  Yanran DING ,  Jinfan ZHANG ,  Chunxu BAI ,  Yong FAN ,  Kaijun SONG ,  Xianqi LIN ,  Bo ZHANG

    IPC: H01Q13/10 ,  H01P3/12 ,  H01Q21/00 ,  H01Q1/48 ,  H01Q9/04 ,  H01Q21/06

    Abstract: A shared-aperture antenna includes a first copper metal layer; a second copper metal layer; and a dielectric substrate layer sandwiched between the first copper metal layer and the second copper metal layer. The dielectric substrate layer includes a plurality of metallized vias. The first copper metal layer is in communication with the second copper metal layer via the plurality of metallized vias. The plurality of metallized vias includes first metallized vias forming an inner circular ring and second metallized vias forming an outer circular ring with respect to the center of the antenna. The first copper metal layer, the dielectric substrate layer, the second copper metal layer, and the first metallized vias form a substrate integrated waveguide (SIW) circular cavity slot antenna. The first copper metal layer, the dielectric substrate layer, the second copper metal layer, the first metallized vias and the second metallized vias form a coaxial cavity slot antenna.

    High Voltage ESD Protection Device
    35.
    发明申请
    High Voltage ESD Protection Device 审中-公开

    公开(公告)号：US20190304966A1

    公开(公告)日：2019-10-03

    申请号：US16017978

    申请日：2018-06-25

    Applicant: University of Electronic Science and Technology of China

    Inventor： Ming QIAO ,  Zhao QI ,  Jiamu XIAO ,  Longfei LIANG ,  Danye LIANG ,  Bo ZHANG

    IPC: H01L27/02 ,  H01L29/10 ,  H01L29/78 ,  H01L29/08

    Abstract: The present invention provides a high voltage ESD protection device including a P-type substrate; a first NWELL region located on the left of the upper part of the P-type substrate; an NP contact region located on the upper part of the first NWELL region; an N+ contact region located on the right of the upper part of the P-type substrate apart from the first NWELL region; a P+ contact region tangential to the right side of the N+ contact region; a NTOP layer arranged on the right of the NP contact region inside the first NWELL region. The NP contact region is connected to a metal piece to form a metal anode. The N+ contact region and the P+ contact region are connected by a metal piece to form a metal cathode.

    LOW-DROPOUT REGULATOR WITH DYNAMIC POLE TRACKING CIRCUIT FOR IMPROVED STABILITY
    37.
    发明申请
    LOW-DROPOUT REGULATOR WITH DYNAMIC POLE TRACKING CIRCUIT FOR IMPROVED STABILITY 有权

    公开(公告)号：US20180046212A1

    公开(公告)日：2018-02-15

    申请号：US15387678

    申请日：2016-12-22

    Applicant: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA

    Inventor： Xin MING ,  Tiansheng LI ,  Jun XU ,  Zhuo WANG ,  Bo ZHANG

    IPC: G05F1/575

    CPC classification number: G05F1/575 ,  G05F1/563 ,  G05F1/565

    Abstract: A low-dropout regulator, including: a dynamic pole tracking circuit having an active load, a voltage-to-current converter, a current amplifier, a bias circuit, a regulating transistor, a first feedback resistor, a second feedback resistor, and a first capacitor. The dynamic pole tracking circuit includes: a first PMOS, a second PMOS, a first resistor, and a second resistor. The voltage-to-current converter includes: a first NMOS, a second NMOS, a third NMOS, a fourth NMOS, a fifth NMOS, a sixth NMOS, a seventh NMOS, an eighth NMOS, a third PMOS, a fourth PMOS, a seventh PMOS, an eighth PMOS. The current amplifier includes: a fifth PMOS, a sixth PMOS, a ninth NMOS, a tenth NMOS, and a third resistor. The bias circuit includes: a ninth PMOS, a tenth PMOS, an eleventh PMOS, an eleventh NMOS, a twelfth NMOS, a thirteenth NMOS, and a fourth resistor.

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