公开(公告)号：US09507942B2

公开(公告)日：2016-11-29

申请号：US14079087

申请日：2013-11-13

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry

IPC: G06F21/57

CPC classification number: G06F21/572 ,  G06F2221/2139

Abstract: An apparatus including a ROM and a microprocessor. The ROM includes BIOS contents that are stored as plaintext and an encrypted digest. The encrypted digest includes an encrypted version of a first digest corresponding to the BIOS contents. The microprocessor is coupled to the BIOS ROM, and includes a tamper timer and a tamper detector. The tamper timer periodically generates an interrupt at a prescribed interval. The tamper detector accesses the BIOS contents and the encrypted digest upon assertion of the interrupt, and directs the microprocessor to generate a second digest corresponding to the BIOS contents and a decrypted digest corresponding to the encrypted digest using the same algorithms and key that were employed to generate the first digest and the encrypted digest, and compares the second digest with the decrypted digest, and precludes operation of the microprocessor if the second digest and the decrypted digest are not equal.

Abstract translation: 一种包括ROM和微处理器的装置。 ROM包括存储为明文和加密摘要的BIOS内容。 加密摘要包括对应于BIOS内容的第一摘要的加密版本。 微处理器耦合到BIOS ROM，并且包括篡改定时器和篡改检测器。 篡改定时器周期性地以规定的间隔产生中断。 篡改检测器在断言时访问BIOS内容和加密摘要，并引导微处理器使用与使用相同的算法和密钥来生成对应于BIOS内容的第二摘要和对应于加密摘要的解密摘要 生成第一个摘要和加密的摘要，并将第二个摘要与解密的摘要进行比较，如果第二个摘要和解密的摘要不相等，则排除微处理器的操作。

公开(公告)号：US09507404B2

公开(公告)日：2016-11-29

申请号：US14281621

申请日：2014-05-19

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks ,  Brent Bean ,  Stephan Gaskins

IPC: G06F1/00 ,  G06F1/32 ,  G06F12/08 ,  G06F13/24 ,  G06F9/38 ,  G06F9/30 ,  G06F9/44 ,  G06F1/04 ,  G06F1/12

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor includes a plurality of cores, a shared cache memory, and a control unit that individually puts each core to sleep by stopping its clock signal. Each core executes a sleep instruction and responsively makes a respective request of the control unit to put the core to sleep, which the control unit responsively does, and detects when all the cores have made the respective request and responsively wakes up only the last requesting cores. The last core writes back and invalidates the shared cache memory and indicates it has been invalidated and makes a request to the control unit to put the last core back to sleep. The control unit puts the last core back to sleep and continuously keeps the other cores asleep while the last core writes back and invalidates the shared cache memory, indicates the shared cache memory was invalidated, and is put back to sleep.

Abstract translation: 微处理器包括多个核心，共享高速缓冲存储器和控制单元，其通过停止其时钟信号来单独地将每个核心置于睡眠状态。 每个核心执行睡眠指令，并且响应地使控制单元的相应请求将核心置于睡眠状态，控制单元响应地进行该操作，并且检测所有核心何时完成了各自的请求，并且响应地只唤醒最后请求的核心 。 最后一个内核写回并使共享高速缓存内存无效，并指示它已被无效，并向控制单元发出请求以使最后一个核心返回休眠状态。 控制单元将最后一个核心置于休眠状态，并持续保持其他内核处于睡眠状态，同时最后一个内核回写并使共享缓存内存无效，表示共享高速缓存内存无效，并返回睡眠状态。

公开(公告)号：US09372696B2

公开(公告)日：2016-06-21

申请号：US14088620

申请日：2013-11-25

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks ,  Brent Bean

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/30178 ,  G06F9/328 ,  G06F9/3891

Abstract: A microprocessor includes a plurality of memories each configured to hold microcode instructions. At least a first of the plurality of memories is configured to provide M-bit wide words of compressed microcode instructions, and at least a second of the plurality of memories is configured to provide N-bit wide words of uncompressed microcode instructions. M and N are integers greater than zero and N is greater than M. The microprocessor also includes a decompression unit configured to decompress the compressed microcode instructions after being fetched from the at least a first of the plurality of memories and before being executed.

Abstract translation: 微处理器包括多个存储器，每个存储器被配置为保持微码指令。 所述多个存储器中的至少第一个被配置为提供压缩微码指令的M位宽的字，并且所述多个存储器中的至少一个存储器被配置为提供未压缩的微代码指令的N位宽字。 M和N是大于零并且N大于M的整数。微处理器还包括解压缩单元，其被配置为在从多个存储器中的至少第一个存储器中取出并在执行之前解压缩压缩的微代码指令。

公开(公告)号：US09183394B2

公开(公告)日：2015-11-10

申请号：US14079299

申请日：2013-11-13

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry

IPC: G06F11/30 ,  G06F21/57

CPC classification number: G06F21/572

Abstract: An apparatus including a ROM, a selector, and a detector. The ROM has partitions stored as plaintext, and encrypted digests, each comprising an encrypted version of a first digest associated with a corresponding one of the partitions. The selector selects one or more partitions responsive to an interrupt. The detector generates the interrupt at a combination of intervals and event occurrences, and accesses the one or more partitions and corresponding one or more encrypted digests upon assertion of the interrupt, and directs generation of one or more second digests corresponding to the one or more partitions and one or more decrypted digests corresponding to the one or more encrypted digests using the same algorithms and key used to generate the first digest and encrypted digests, and compares the second digests with the decrypted digests, and precludes the operation if the second digests and the decrypted digests are not pair wise equal.

Abstract translation: 一种包括ROM，选择器和检测器的装置。 ROM具有作为明文存储的分区和加密摘要，每个分组包括与对应的一个分区相关联的第一摘要的加密版本。 选择器响应于中断选择一个或多个分区。 检测器以间隔和事件发生的组合产生中断，并且在断言中访问一个或多个分区和对应的一个或多个加密摘要，并且指导与一个或多个分区对应的一个或多个第二摘要的生成 以及使用与生成第一摘要和加密摘要相同的算法和密钥对应于一个或多个加密摘要的一个或多个解密摘要，并将第二摘要与解密的摘要进行比较，并且如果第二摘要和 解密的摘要不是双方平等的。

公开(公告)号：US20150134977A1

公开(公告)日：2015-05-14

申请号：US14079226

申请日：2013-11-13

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry

IPC: G06F21/57

CPC classification number: G06F21/572 ,  G06F21/575 ,  G06F21/64

Abstract: An apparatus including a ROM, a selector, and a detector. The ROM has partitions and encrypted digests. Each of the partitions is stored as plaintext, and each of the encrypted digests includes an encrypted version of a first digest associated with a corresponding one of the partitions. The selector selects one or more of the partitions responsive to an interrupt. The detector accesses the one or more of the partitions and corresponding one or more of the encrypted digests upon assertion of the interrupt, and directs a microprocessor to generate one or more of second digests corresponding to the one or more of the partitions and one or more of decrypted digests corresponding to the one or more of encrypted digests using the same algorithms and key that were employed to generate the first digest and the encrypted digests, and compares the one or more of the second digests with the one or more of the decrypted digests, and precludes operation of the microprocessor if the one or more of the second digests and the one or more of the decrypted digests are not pair wise equal.

Abstract translation: 一种包括ROM，选择器和检测器的装置。 ROM具有分区和加密摘要。 每个分区被存储为明文，并且每个加密的摘要包括与相应的一个分区相关联的第一摘要的加密版本。 选择器响应于中断选择一个或多个分区。 检测器在断言时访问一个或多个分区和对应的一个或多个加密摘要，并指示微处理器生成对应于一个或多个分区和一个或多个分区的一个或多个第二摘要 使用与用于生成第一摘要和加密摘要相同的算法和密钥对应于一个或多个加密摘要的解密摘要，并将第二摘要中的一个或多个与解密的摘要中的一个或多个进行比较 并且如果所述第二摘要中的一个或多个和所解密的摘要中的一个或多个不是成对相等的，则排除所述微处理器的操作。

公开(公告)号：US20150134974A1

公开(公告)日：2015-05-14

申请号：US14079021

申请日：2013-11-13

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry

IPC: G06F21/57

CPC classification number: G06F21/572 ,  G06F2221/2107

Abstract: An apparatus including a BIOS read only memory (ROM) and a tamper detector. The BIOS ROM includes BIOS contents stored as plaintext, and an encrypted message digest comprising an encrypted version of a first message digest that corresponds to the BIOS contents. The tamper detector is coupled to the BIOS ROM, and accesses the BIOS contents and the encrypted message digest upon reset of a microprocessor, and directs the microprocessor to generate a second message digest corresponding to the BIOS contents and a decrypted message digest corresponding to the encrypted message digest using the same algorithms and key that were employed to generate the first message digest and the encrypted message digest, and compares the second message digest with the decrypted message digest, and precludes the operation of the microprocessor if the second message digest and the decrypted message digest are not equal.

Abstract translation: 一种包括BIOS只读存储器（ROM）和篡改检测器的设备。 BIOS ROM包括存储为明文的BIOS内容和包含对应于BIOS内容的第一消息摘要的加密版本的加密消息摘要。 篡改检测器耦合到BIOS ROM，并且在微处理器复位时访问BIOS内容和加密消息摘要，并引导微处理器生成对应于BIOS内容的第二消息摘要和对应于加密的解密消息摘要 消息摘要，使用与用于生成第一消息摘要和加密消息摘要相同的算法和密钥，并将第二消息摘要与解密的消息摘要进行比较，并且如果第二消息摘要和解密则排除微处理器的操作 消息摘要不相等。

公开(公告)号：US20150067214A1

公开(公告)日：2015-03-05

申请号：US14281621

申请日：2014-05-19

Applicant: VIA Technologies, Inc.

Inventor： G. Glenn Henry ,  Terry Parks ,  Brent Bean ,  Stephan Gaskins

IPC: G06F1/32 ,  G06F13/24 ,  G06F12/08

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor includes a plurality of cores, a shared cache memory, and a control unit that individually puts each core to sleep by stopping its clock signal. Each core executes a sleep instruction and responsively makes a respective request of the control unit to put the core to sleep, which the control unit responsively does, and detects when all the cores have made the respective request and responsively wakes up only the last requesting cores. The last core writes back and invalidates the shared cache memory and indicates it has been invalidated and makes a request to the control unit to put the last core back to sleep. The control unit puts the last core back to sleep and continuously keeps the other cores asleep while the last core writes back and invalidates the shared cache memory, indicates the shared cache memory was invalidated, and is put back to sleep.

Abstract translation: 微处理器包括多个核心，共享高速缓冲存储器和控制单元，其通过停止其时钟信号来单独地将每个核心置于睡眠状态。 每个核心执行睡眠指令，并且响应地使控制单元的相应请求将核心置于睡眠状态，控制单元响应地进行该操作，并且检测所有核心何时完成了各自的请求，并且响应地只唤醒最后请求的核心 。 最后一个内核写回并使共享高速缓存内存无效，并指示它已被无效，并向控制单元发出请求以使最后一个核心返回休眠状态。 控制单元将最后一个核心置于休眠状态，并持续保持其他内核处于睡眠状态，同时最后一个内核回写并使共享缓存内存无效，表示共享高速缓存内存无效，并返回睡眠状态。

公开(公告)号：US20150054543A1

公开(公告)日：2015-02-26

申请号：US13972690

申请日：2013-08-21

Applicant: Via Technologies, Inc.

Inventor： G. Glenn Henry ,  Dinesh K. Jain

IPC: G11C17/16

CPC classification number: G11C17/16 ,  G06F15/7807

Abstract: An apparatus includes a fuse array, a random access memory (RAM), and a plurality of cores. The fuse array is disposed on a die, where the fuse array has a plurality of semiconductor fuses programmed with compressed configuration data. The RAM is disposed separately on the die. The plurality of cores is disposed separately on the die, where each of the plurality of cores is coupled to the fuse array and the RAM, and where the each of the plurality of cores accesses either the fuse array or the RAM upon power-up/reset as indicated by contents of a load data register to obtain the compressed configuration data.

Abstract translation: 一种装置包括熔丝阵列，随机存取存储器（RAM）和多个核。 熔丝阵列设置在管芯上，其中熔丝阵列具有多个半导体保险丝，其被编程有压缩的配置数据。 RAM分开设置在模具上。 多个芯分别设置在管芯上，其中多个芯中的每个芯耦合到熔丝阵列和RAM，并且其中多个芯中的每一个在上电/下电时访问熔丝阵列或RAM， 由负载数据寄存器的内容指示复位以获得压缩的配置数据。

公开(公告)号：US08850229B2

公开(公告)日：2014-09-30

申请号：US14066270

申请日：2013-10-29

Applicant: VIA Technologies, Inc.

Inventor： G. Glenn Henry ,  Terry Parks ,  Brent Bean ,  Thomas A. Crispin

IPC: G06F21/00 ,  G06F21/71 ,  G06F9/30 ,  H04L9/08 ,  G06F21/52 ,  G06F21/60 ,  G06F12/08 ,  G06F21/54 ,  H04L9/06 ,  G06F21/72

CPC classification number: H04L9/0827 ,  G06F9/30003 ,  G06F9/30079 ,  G06F9/30178 ,  G06F9/30189 ,  G06F12/0875 ,  G06F21/52 ,  G06F21/54 ,  G06F21/602 ,  G06F21/71 ,  G06F21/72 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2221/2107 ,  H04L9/0618 ,  H04L9/0861 ,  H04L9/0891 ,  H04L9/0894 ,  H04L2209/12 ,  H04L2209/20

Abstract: An apparatus for generating a decryption key for use to decrypt a block of encrypted instruction data being fetched from an instruction cache in a microprocessor at a fetch address includes a first multiplexer that selects a first key value from a plurality of key values based on a first portion of the fetch address. A second multiplexer selects a second key value from the plurality of key values based on the first portion of the fetch address. A rotater rotates the first key value based on a second portion of the fetch address. An arithmetic unit selectively adds or subtracts the rotated first key value to or from the second key value based on a third portion of the fetch address to generate the decryption key.

Abstract translation: 一种用于产生解密密钥的装置，用于解密从提取地址的微处理器中的指令高速缓存取出的加密指令数据块，其包括：第一多路复用器，其基于第一和第二多个键值从多个键值中选择第一键值 提取地址的一部分。 第二多路复用器根据提取地址的第一部分从多个键值中选择第二键值。 旋转器基于获取地址的第二部分旋转第一键值。 算术单元基于获取地址的第三部分，有选择地向第二密钥值添加或减去所转动的第一密钥值，以生成解密密钥。

公开(公告)号：US20140195823A1

公开(公告)日：2014-07-10

申请号：US14066485

申请日：2013-10-29

Applicant: VIA Technologies, Inc.

Inventor： G. Glenn Henry ,  Terry Parks ,  Brent Bean ,  Thomas A. Crispin

IPC: G06F21/54

CPC classification number: H04L9/0827 ,  G06F9/30003 ,  G06F9/30079 ,  G06F9/30178 ,  G06F9/30189 ,  G06F12/0875 ,  G06F21/52 ,  G06F21/54 ,  G06F21/602 ,  G06F21/71 ,  G06F21/72 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2221/2107 ,  H04L9/0618 ,  H04L9/0861 ,  H04L9/0891 ,  H04L9/0894 ,  H04L2209/12 ,  H04L2209/20

Abstract: A microprocessor includes an architected register having a bit. The microprocessor sets the bit. The microprocessor also includes a fetch unit that fetches encrypted instructions from an instruction cache and decrypts them prior to executing them, in response to the microprocessor setting the bit. The microprocessor saves the value of the bit to a stack in memory and then clears the bit, in response to receiving an interrupt. The fetch unit fetches unencrypted instructions from the instruction cache and executes them without decrypting them, after the microprocessor clears the bit. The microprocessor restores the saved value from the stack in memory to the bit in the architected register, in response to executing a return from interrupt instruction. The fetch unit resumes fetching and decrypting the encrypted instructions, in response to determining that the restored value of the bit is set.

Abstract translation: 微处理器包括具有一定位的架构化寄存器。 微处理器设置位。 微处理器还包括提取单元，其响应于微处理器设置该位，从指令高速缓存取出加密指令并在执行它们之前对其进行解密。 微处理器将该位的值保存到存储器中的堆栈，然后清除该位，以响应接收到中断。 提取单元从指令高速缓存中读取未加密的指令，并在微处理器清零位之后执行它们而不对其进行解密。 微处理器将保存的值从存储器中的堆栈恢复到架构化寄存器中的位，以响应执行中断指令的返回。 响应于确定该位的恢复值被设置，获取单元恢复获取和解密加密指令。