公开(公告)号：US5939334A

公开(公告)日：1999-08-17

申请号：US861808

申请日：1997-05-22

申请人： Tue Nguyen ,  Lawrence J. Charneski ,  David R. Evans ,  Sheng Teng Hsu

发明人： Tue Nguyen ,  Lawrence J. Charneski ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： C23F1/12 ,  C23G5/00 ,  H01L21/302 ,  H01L21/304 ,  H01L21/306 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768

CPC分类号： C23G5/00 ,  H01L21/02063 ,  H01L21/31111 ,  H01L21/31138 ,  H01L21/32134 ,  H01L21/76838 ,  H01L21/02068

摘要： A system and method of selectively etching copper surfaces free of copper oxides in preparation for the deposition of an interconnecting metallic material is provided. The method removes metal oxides with .beta.-diketones, such as Hhfac. The Hhfac is delivered into the system in vapor form, and reacts almost exclusively to copper oxides. The by-products of the cleaning process are likewise volatile for removal from the system with a vacuum pressure. Since the process is easily adaptable to most IC process systems, it can be conducted in an oxygen-free environment, without the removal of the IC from the process chamber. The in-situ cleaning process permits a minimum amount of copper oxide to reform before the deposition of the overlying interconnection metal. In this manner, a highly conductive electrical interconnection between the copper surface and the interconnecting metal material is formed. An IC having a metal interconnection, in which the underlying copper layer is cleaned of copper oxides, in-situ with Hhfac vapor, is also provided.

摘要翻译： 提供了一种选择性地蚀刻不含铜氧化物的铜表面以准备沉积互连金属材料的系统和方法。 该方法用β-二酮如Hhfac除去金属氧化物。 Hhfac以蒸气形式输送到系统中，几乎完全与铜氧化物反应。 清洁过程的副产物同样是挥发性的，用于在真空压力下从系统中除去。 由于该方法很容易适用于大多数IC工艺系统，所以它可以在无氧环境下进行，而不会从处理室中移除IC。 在沉积互连金属之前，原位清洁工艺允许最小量的氧化铜重整。 以这种方式，形成铜表面和互连金属材料之间的高导电性电互连。 还提供了具有金属互连的IC，其中下面的铜层用Hhfac蒸气原位清除了铜氧化物。

公开(公告)号：US07696550B2

公开(公告)日：2010-04-13

申请号：US11805177

申请日：2007-05-22

申请人： Tingkai Li ,  Lawrence J. Charneski ,  Wei-Wei Zhuang ,  David R. Evans ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Lawrence J. Charneski ,  Wei-Wei Zhuang ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： H01L29/76

CPC分类号： H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1616

摘要： A multi-layer PrxCa1-xMnO3 (PCMO) thin film capacitor and associated deposition method are provided for forming a bipolar switching thin film. The method comprises: forming a bottom electrode; depositing a nanocrystalline PCMO layer; depositing a polycrystalline PCMO layer; forming a multi-layer PCMO film with bipolar switching properties; and, forming top electrode overlying the PCMO film. If the polycrystalline layers are deposited overlying the nanocrystalline layers, a high resistance can be written with narrow pulse width, negative voltage pulses. The PCMO film can be reset to a low resistance using a narrow pulse width, positive amplitude pulse. Likewise, if the nanocrystalline layers are deposited overlying the polycrystalline layers, a high resistance can be written with narrow pulse width, positive voltage pulses, and reset to a low resistance using a narrow pulse width, negative amplitude pulse.

摘要翻译： 提供多层PrxCa1-xMnO3（PCMO）薄膜电容器和相关的沉积方法用于形成双极开关薄膜。 该方法包括：形成底部电极; 沉积纳米晶体PCMO层; 沉积多晶PCMO层; 形成具有双极开关特性的多层PCMO膜; 并且形成覆盖PCMO膜的顶部电极。 如果多晶层沉积在纳米晶层之上，则可以用窄脉冲宽度，负电压脉冲写入高电阻。 PCMO膜可以使用窄脉冲宽度，正幅度脉冲复位为低电阻。 同样，如果纳米晶层沉积在多晶层上，则可以用窄脉冲宽度，正电压脉冲写入高电阻，并使用窄脉冲宽度，负幅度脉冲将其复位为低电阻。

公开(公告)号：US07446010B2

公开(公告)日：2008-11-04

申请号：US11435669

申请日：2006-05-17

申请人： Tingkai Li ,  Sheng Teng Hsu ,  David R. Evans

发明人： Tingkai Li ,  Sheng Teng Hsu ,  David R. Evans

IPC分类号： H01L21/8222

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C2213/31 ,  H01L27/2409 ,  H01L29/66143 ,  H01L29/872 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： A method is provided for forming a metal/semiconductor/metal (MSM) back-to-back Schottky diode from a silicon (Si) semiconductor. The method deposits a Si semiconductor layer between a bottom electrode and a top electrode, and forms a MSM diode having a threshold voltage, breakdown voltage, and on/off current ratio. The method is able to modify the threshold voltage, breakdown voltage, and on/off current ratio of the MSM diode in response to controlling the Si semiconductor layer thickness. Generally, both the threshold and breakdown voltage are increased in response to increasing the Si thickness. With respect to the on/off current ratio, there is an optimal thickness. The method is able to form an amorphous Si (a-Si) and polycrystalline Si (polySi) semiconductor layer using either chemical vapor deposition (CVD) or DC sputtering. The Si semiconductor can be doped with a Group V donor material, which decreases the threshold voltage and increases the breakdown voltage.

摘要翻译： 提供了用于从硅（Si）半导体形成金属/半导体/金属（MSM）背对背肖特基二极管的方法。 该方法在底电极和顶电极之间沉积Si半导体层，并形成具有阈值电压，击穿电压和开/关电流比的MSM二极管。 响应于控制Si半导体层厚度，该方法能够修改MSM二极管的阈值电压，击穿电压和导通/截止电流比。 通常，响应于Si厚度的增加，阈值和击穿电压都增加。 关于开/关电流比，存在最佳厚度。 该方法能够使用化学气相沉积（CVD）或DC溅射形成非晶Si（a-Si）和多晶硅（polySi）半导体层。 Si半导体可以掺杂有V族施主材料，其降低阈值电压并增加击穿电压。

公开(公告)号：US06992025B2

公开(公告)日：2006-01-31

申请号：US10755615

申请日：2004-01-12

申请人： Jer-shen Maa ,  Jong-Jan Lee ,  Douglas J. Tweet ,  David R. Evans ,  Allen W. Burmaster ,  Sheng Teng Hsu

发明人： Jer-shen Maa ,  Jong-Jan Lee ,  Douglas J. Tweet ,  David R. Evans ,  Allen W. Burmaster ,  Sheng Teng Hsu

IPC分类号： H01L21/26 ,  H01L21/42 ,  H01L21/324

CPC分类号： H01L21/76254

摘要： Transistors fabricated on SSOI (Strained Silicon On Insulator) substrate, which comprises a strained silicon layer disposed directly on an insulator layer, have enhanced device performance due to the strain-induced band modification of the strained silicon device channel and the limited silicon volume because of the insulator layer. The present invention discloses a SSOI substrate fabrication process comprising various novel approaches. One is the use of a thin relaxed SiGe layer as the strain-induced seed layer to facilitate integration and reduce processing cost. Another is the formation of split implant microcracks deep in the silicon substrate to reduce the number of threading dislocations reaching the strained silicon layer. And lastly is the two step annealing/thinning process for the strained silicon/SiGe multilayer film transfer without blister or flaking formation.

摘要翻译： 包含直接设置在绝缘体层上的应变硅层的SSOI（应变绝缘体硅）基板上制造的晶体管由于应变诱导的应变硅器件通道的带隙修改而增加了器件性能，并且由于 绝缘体层。 本发明公开了一种包含各种新颖方法的SSOI衬底制造工艺。 一个是使用薄的松弛SiGe层作为应变诱导的种子层，以促进整合并降低加工成本。 另一个是在硅衬底深部形成分裂的植入物微裂纹，以减少到达应变硅层的穿透位错的数量。 最后是对应变硅/ SiGe多层膜转移的两步退火/变薄处理，没有起泡或剥落形成。

公开(公告)号：US06972239B1

公开(公告)日：2005-12-06

申请号：US10923529

申请日：2004-08-20

申请人： Tingkai Li ,  Wei-Wei Zhuang ,  Lawrence J. Charneski ,  David R. Evans ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Wei-Wei Zhuang ,  Lawrence J. Charneski ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： C23C16/40 ,  H01L21/20 ,  H01L45/00

CPC分类号： H01L45/1616 ,  C23C16/40 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： A method of fabricating a PCMO thin film at low temperature for use in a RRAM device includes preparing a PCMO precursor; preparing a substrate; placing the substrate into a MOCVD chamber; introducing the PCMO precursor into the MOCVD chamber to deposit a PCMO thin film on the substrate; maintaining a MOCVD vaporizer at between about 240° C. to 280° C. and maintaining the MOCVD chamber at a temperature of between about 300° C. to 400° C.; removing the PCMO thin-film bearing substrate from the MOCVD chamber; and completing the RRAM device.

摘要翻译： 在低温下制造用于RRAM器件的PCMO薄膜的方法包括制备PCMO前体; 制备底物; 将基板放置在MOCVD室中; 将PCMO前体引入MOCVD室以在衬底上沉积PCMO薄膜; 将MOCVD蒸发器保持在约240℃至280℃之间并将MOCVD室保持在约300℃至400℃之间的温度下; 从MOCVD室中取出PCMO薄膜轴承衬底; 并完成RRAM设备。

公开(公告)号：US06774054B1

公开(公告)日：2004-08-10

申请号：US10640728

申请日：2003-08-13

申请人： Fengyan Zhang ,  Wei-Wei Zhuang ,  David R. Evans ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Wei-Wei Zhuang ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： H01L2131

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  H01L21/31691 ,  H01L28/20 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1608

摘要： A method of forming a PCMO thin film in a RRAM device includes preparing a substrate; depositing a metal barrier layer on the substrate; forming a bottom electrode on the barrier layer; spin-coating a layer of Pr1−xCaxMnO3 (PCMO) on the bottom electrode using a PCMO precursor; baking the PCMO thin film in one or more baking steps; annealing the PCMO thin film in a first annealing step after each spin-coating step; repeating the spin-coating step, the baking step and the first annealing step until the PCMO thin film has a desired thickness; annealing the PCMO thin film in a second annealing step, thereby producing a PCMO thin film having a crystalline structure of Pr1−xCaxMnO3, where 0.2

摘要翻译： 在RRAM器件中形成PCMO薄膜的方法包括：制备衬底; 在衬底上沉积金属阻挡层; 在阻挡层上形成底部电极; 使用PCMO前体在底部电极上旋涂一层Pr1-xCaxMnO3（PCMO）; 在一个或多个烘烤步骤中烘烤PCMO薄膜; 在每个旋涂步骤之后的第一退火步骤中对PCMO薄膜进行退火; 重复旋涂步骤，烘烤步骤和第一退火步骤直到PCMO薄膜具有所需厚度; 在第二退火步骤中退火PCMO薄膜，从而制备具有Pr1-xCaxMnO3晶体结构的PCMO薄膜，其中0.2 <= X <= 0.5; 沉积顶部电极; 图案化顶部电极; 并完成RRAM设备。

公开(公告)号：US06716691B1

公开(公告)日：2004-04-06

申请号：US10606105

申请日：2003-06-25

申请人： David R. Evans ,  Sheng Teng Hsu ,  Bruce D. Ulrich ,  Douglas J. Tweet ,  Lisa H. Stecker

发明人： David R. Evans ,  Sheng Teng Hsu ,  Bruce D. Ulrich ,  Douglas J. Tweet ,  Lisa H. Stecker

IPC分类号： H01L218238

CPC分类号： H01L21/76224 ,  H01L21/28123 ,  H01L21/823878

摘要： A method of fabricating a CMOS have self-aligned shallow trench isolation, includes preparing a silicon substrate; forming a gate stack; depositing a layer of first polysilicon; trenching the substrate by shallow trench isolation to form a trench; filling the trench with oxide; depositing a second layer of polysilicon wherein the top surface of the second polysilicon layer is above the top surface of the first polysilicon layer; depositing a sacrificial oxide layer having a thickness of at least 1.5× that of the first polysilicon layer; CMP the sacrificial oxide layer to the level of the upper surface of the second polysilicon layer; depositing a third layer of polysilicon; patterning and etching the gate stack; implanting ions to form a source region, a drain region and the polysilicon gate; and completing the CMOS structure.

摘要翻译： 制造CMOS的方法具有自对准浅沟槽隔离，包括制备硅衬底; 形成栅极叠层; 沉积第一多晶硅层; 通过浅沟槽隔离对衬底进行沟槽以形成沟槽; 用氧化物填充沟槽; 沉积第二多晶硅层，其中第二多晶硅层的顶表面在第一多晶硅层的顶表面之上; 沉积厚度至少为第一多晶硅层的1.5倍的牺牲氧化物层; 将牺牲氧化物层CMP CMP化为第二多晶硅层的上表面的水平; 沉积第三层多晶硅; 图案化和蚀刻栅极堆叠; 注入离子以形成源极区，漏极区和多晶硅栅; 并完成CMOS结构。

公开(公告)号：US06669870B2

公开(公告)日：2003-12-30

申请号：US09820024

申请日：2001-03-28

申请人： Wei-Wei Zhuang ,  Tue Nguyen ,  Lawrence J. Charneski ,  David R. Evans ,  Sheng Teng Hsu

发明人： Wei-Wei Zhuang ,  Tue Nguyen ,  Lawrence J. Charneski ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： H01B102

CPC分类号： C23C16/18

摘要： A Cu(hfac) precursor with a substituted phenylethylene ligand has been provided. The substituted phenylethylene ligand includes bonds to molecules selected from the group consisting of C1 to C6 alkyl, C1 to C6 haloalkyl, C1 to C6 phenyl, H and C1 to C6 alkoxyl. One variation, the &agr;-methylstyrene ligand precursor has proved to be stable a low temperatures, and sufficiently volatile at higher temperatures. Copper deposited with this precursor has low resistivity and high adhesive characteristics. A synthesis method has been provided which produces a high yield of the above-described precursor.

摘要翻译： 已经提供了具有取代的苯基乙炔配体的Cu（hfac）前体。 取代的苯基乙炔配体包括与选自C1至C6烷基，C1至C6卤代烷基，C1至C6苯基，H和C1至C6烷氧基的分子的键。 已经证明α-甲基苯乙烯配体前体的一个变化是在低温下是稳定的，并且在较高温度下具有足够的挥发性。 沉积有该前体的铜具有低电阻率和高粘合特性。 已经提供了产生高产率的上述前体的合成方法。

公开(公告)号：US06596344B2

公开(公告)日：2003-07-22

申请号：US09820227

申请日：2001-03-27

申请人： Wei-Wei Zhuang ,  Lawrence J. Charneski ,  David R. Evans ,  Sheng Teng Hsu

发明人： Wei-Wei Zhuang ,  Lawrence J. Charneski ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： C23C1614

CPC分类号： H01L21/28556 ,  C23C16/18

摘要： A method for chemical vapor deposition of copper metal thin film on a substrate includes heating a substrate onto which the copper metal thin film is to be deposited in a chemical vapor deposition chamber; vaporizing a precursor containing the copper metal, wherein the precursor is a compound of (&agr;-methylstyrene)Cu(I)(hfac), where hfac is hexafluoroacetylacetonate, and (hfac)Cu(I)L, where L is an alkene; introducing the vaporized precursor into the chemical vapor deposition chamber adjacent the heated substrate; and condensing the vaporized precursor onto the substrate thereby depositing copper metal onto the substrate. A copper metal precursor for use in the chemical vapor deposition of a copper metal thin film is a compound of (&agr;-methylstyrene)Cu(I)(hfac), where hfac is hexafluoroacetylacetonate, and (hfac)Cu(I)L, where L is an alkene taken from the group of alkenes consisting of 1-pentene, 1-hexene and trimethylvinylsilane.

公开(公告)号：US06303502B1

公开(公告)日：2001-10-16

申请号：US09588940

申请日：2000-06-06

申请人： Sheng Teng Hsu ,  David R. Evans ,  Tingkai Li ,  Jer-shen Maa ,  Wei-Wei Zhuang

发明人： Sheng Teng Hsu ,  David R. Evans ,  Tingkai Li ,  Jer-shen Maa ,  Wei-Wei Zhuang

IPC分类号： H01L2144

CPC分类号： H01L21/28291 ,  H01L29/78391

摘要： A method of fabricating a one-transistor memory includes, on a single crystal silicon substrate, depositing a bottom electrode structure on a gate oxide layer; implanting ions to form a source region and a drain region and activating the implanted ions spin coating the structure with a first ferroelectric layer; depositing a second ferroelectric layer; and annealing the structure to provide a c-axis ferroelectric orientation.

摘要翻译： 制造单晶体管存储器的方法包括在单晶硅衬底上，在栅氧化层上沉积底电极结构; 注入离子以形成源极区域和漏极区域并激活注入的离子旋转涂覆第一铁电层的结构; 沉积第二铁电层; 并退火该结构以提供c轴铁电取向。