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    NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    32.
    发明申请
    NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US20120132879A1

    公开(公告)日：2012-05-31

    申请号：US13366544

    申请日：2012-02-06

    申请人： MASAHARU KINOSHITA ,  Yoshitaka Sasago ,  Norikatsu Takaura

    发明人： MASAHARU KINOSHITA ,  Yoshitaka Sasago ,  Norikatsu Takaura

    IPC分类号： H01L45/00

    CPC分类号： H01L45/144 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/1675 ,  Y10S438/90

    摘要： Provided is a nonvolatile memory device including a phase-change memory configured with cross-point memory cells in which memory elements formed of a phase-change material and selection elements formed with a diode are combined. A memory cell is configured with a memory element formed of a phase-change material and a selection element formed with a diode having a stacked structure of a first polycrystalline silicon film, a second polycrystalline silicon film, and a third polycrystalline silicon film. The memory cells are arranged at intersection points of a plurality of first metal wirings extending along a first direction with a plurality of third metal wirings extending along a second direction orthogonal to the first direction. An interlayer film is formed between adjacent selection elements and between adjacent memory elements, and voids are formed in the interlayer film provided between the adjacent memory elements.

    摘要翻译： 本发明提供一种非易失性存储装置，其包括：配置有交叉点存储单元的相变存储器，其中由相变材料形成的存储元件和由二极管形成的选择元件组合。 存储单元配置有由相变材料形成的存储元件和由具有第一多晶硅膜，第二多晶硅膜和第三多晶硅膜的堆叠结构的二极管形成的选择元件。 存储单元布置在沿着第一方向延伸的多个第一金属布线的交点和沿着与第一方向正交的第二方向延伸的多个第三金属布线。 在相邻的选择元件之间和相邻的存储元件之间形成中间膜，并且在设置在相邻的存储元件之间的层间膜中形成空隙。

    Nonvolatile memory device and method of manufacturing the same
    33.
    发明授权
    Nonvolatile memory device and method of manufacturing the same 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US08129705B2

    公开(公告)日：2012-03-06

    申请号：US12434633

    申请日：2009-05-02

    申请人： Masaharu Kinoshita ,  Yoshitaka Sasago ,  Norikatsu Takaura

    发明人： Masaharu Kinoshita ,  Yoshitaka Sasago ,  Norikatsu Takaura

    IPC分类号： H01L45/00

    CPC分类号： H01L45/144 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/1675 ,  Y10S438/90

    摘要： Provided is a nonvolatile memory device including a phase-change memory configured with cross-point memory cells in which memory elements formed of a phase-change material and selection elements formed with a diode are combined. A memory cell is configured with a memory element formed of a phase-change material and a selection element formed with a diode having a stacked structure of a first polycrystalline silicon film, a second polycrystalline silicon film, and a third polycrystalline silicon film. The memory cells are arranged at intersection points of a plurality of first metal wirings extending along a first direction with a plurality of third metal wirings extending along a second direction orthogonal to the first direction. An interlayer film is formed between adjacent selection elements and between adjacent memory elements, and voids are formed in the interlayer film provided between the adjacent memory elements.

    摘要翻译： 本发明提供一种非易失性存储装置，其包括：配置有交叉点存储单元的相变存储器，其中由相变材料形成的存储元件和由二极管形成的选择元件组合。 存储单元配置有由相变材料形成的存储元件和由具有第一多晶硅膜，第二多晶硅膜和第三多晶硅膜的堆叠结构的二极管形成的选择元件。 存储单元布置在沿着第一方向延伸的多个第一金属布线的交点和沿着与第一方向正交的第二方向延伸的多个第三金属布线。 在相邻的选择元件之间和相邻的存储元件之间形成中间膜，并且在设置在相邻的存储元件之间的层间膜中形成空隙。

    Semiconductor memory device
    37.
    发明申请
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US20070109870A1

    公开(公告)日：2007-05-17

    申请号：US11652023

    申请日：2007-01-11

    申请人： Hideaki Kurata ,  Kazuo Otsuga ,  Yoshitaka Sasago ,  Takashi Kobayashi ,  Tsuyoshi Arigane

    发明人： Hideaki Kurata ,  Kazuo Otsuga ,  Yoshitaka Sasago ,  Takashi Kobayashi ,  Tsuyoshi Arigane

    IPC分类号： G11C16/04

    CPC分类号： H01L27/11521 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/12 ,  G11C16/3459 ,  H01L27/115 ,  H01L27/11524

    摘要： Suppressing a leakage current is required in a flash memory because the channel length is made shorter with a reduction in the memory cell size. In an AND type memory array having an assist electrode, although the memory cell area has been reduced by the field isolation using a MOS transistor, leakage current in the channel direction becomes greater with a reduction in the memory cell size, resulting in problems arising like deterioration of programming characteristics, an increase in the current consumption, and reading failure. To achieve the objective, in the present invention, electrical isolation is performed by controlling at least one assist electrode of the assist electrodes wired in parallel to be a negative voltage during program and read operations and by making the semiconductor substrate surface in the vicinity of the aforementioned assist electrode non-conductive.

    摘要翻译： 在闪速存储器中需要抑制泄漏电流，因为随着存储器单元尺寸的减小，通道长度变短。 在具有辅助电极的AND型存储器阵列中，虽然通过使用MOS晶体管的场隔离来减小存储单元面积，但是由于存储单元尺寸的减小，沟道方向的泄漏电流变大，导致出现像 编程特性恶化，电流消耗增加，读取失败。 为了实现该目的，在本发明中，通过在编程和读取操作期间将辅助电极并联布置的至少一个辅助电极作为负电压进行电隔离，并且通过使半导体衬底表面在 上述辅助电极不导电。

    Semiconductor device and method of manufacturing the same
    38.
    发明授权
    Semiconductor device and method of manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US07190017B2

    公开(公告)日：2007-03-13

    申请号：US11022773

    申请日：2004-12-28

    申请人： Yoshitaka Sasago ,  Takashi Kobayashi

    发明人： Yoshitaka Sasago ,  Takashi Kobayashi

    IPC分类号： H01L29/76

    CPC分类号： H01L27/11526 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11531

    摘要： Reliability of a semiconductor device having a nonvolatile memory comprising first through third gate electrodes is enhanced. With a flash memory having first gate electrodes (floating gate electrodes), second gate electrodes (control gate electrodes) and third gate electrodes, isolation parts are formed in a self-aligned manner against patterns of a conductor film for forming the third gate electrodes by filling up the respective isolation grooves and a gate insulator film for select nMISes in a peripheral circuit region is formed prior to the formation of the isolation parts. By so doing, deficiency with the gate insulator film for the select nMISes, caused by stress occurring to the isolation parts, can be reduced. Further, with the semiconductor device including the case of stacked memory cells, the patterns of the conductor film for forming the third gate electrodes, serving as a mask for forming the isolation parts in the self-aligned manner, can be formed without misalignment against channels.

    摘要翻译： 具有包括第一至第三栅电极的非易失性存储器的半导体器件的可靠性得到增强。 利用具有第一栅电极（浮栅电极），第二栅电极（控制栅电极）和第三栅电极的闪速存储器，隔离部分以自对准的方式形成，以抵抗用于形成第三栅电极的导体膜的图案 填充相应的隔离沟槽，并且在形成隔离部件之前形成用于在外围电路区域中选择的nMIS的栅极绝缘膜。 通过这样做，可以减少由隔离部分发生的应力引起的用于选择性nMIS的栅极绝缘膜的缺陷。 此外，通过包括堆叠的存储单元的情况的半导体器件，可以形成用作形成隔离部件的自对准方式的掩模的用于形成第三栅电极的导体膜的图案，而不对准通道 。

    Nonvolatile semiconductor memory device and manufacturing method thereof
    40.
    发明申请
    Nonvolatile semiconductor memory device and manufacturing method thereof 审中-公开
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US20060001081A1

    公开(公告)日：2006-01-05

    申请号：US11166114

    申请日：2005-06-27

    申请人： Yoshitaka Sasago ,  Takashi Kobayashi ,  Naohiro Hosoda ,  Tetsuo Adachi ,  Masataka Kato

    发明人： Yoshitaka Sasago ,  Takashi Kobayashi ,  Naohiro Hosoda ,  Tetsuo Adachi ,  Masataka Kato

    IPC分类号： H01L29/788

    CPC分类号： H01L27/115 ,  G11C16/0433 ,  G11C16/0491 ,  H01L27/11521

    摘要： A leakage current flowing between data lines of a nonvolatile semiconductor memory is reduced. In a memory array of a nonvolatile semiconductor memory device having an AND type flash memory, a concave portion is formed in a junction isolation area between adjacent word limes and between adjacent assist gate wirings AGL, and the height of a main surface (first main surface) of a semiconductor substrate in the region where the concave portion is formed is made lower than that of the main surface (second main surface) of the semiconductor substrate to which an assist gate wiring is facing. As a result, it is possible to control the leakage current that flows between the drain line and source line in the aforementioned junction isolation region during operation of a flash memory.

    摘要翻译： 在非易失性半导体存储器的数据线之间流动的漏电流减少。 在具有AND型闪速存储器的非易失性半导体存储器件的存储器阵列中，在相邻字灰度之间和相邻辅助栅极布线AGL之间的结隔离区域中形成凹部，并且在主表面（第一主表面 ）形成在形成有凹部的区域中的半导体衬底的低于辅助栅极布线所面对的半导体衬底的主表面（第二主表面）的厚度。 结果，可以在闪速存储器的操作期间控制在上述结隔离区域中的漏极线和源极线之间流动的漏电流。