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46 条记录 (耗时 0.018 秒)

    Method of making a high-voltage, low on-resistance IgFET
    34.
    发明授权
    Method of making a high-voltage, low on-resistance IgFET 失效
    制造高电压，低电阻IGFET的方法

    公开(公告)号：US5057445A

    公开(公告)日：1991-10-15

    申请号：US639767

    申请日：1991-01-11

    申请人： Ching F. Yeh ,  Yuji Yatsuda

    发明人： Ching F. Yeh ,  Yuji Yatsuda

    IPC分类号： H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

    CPC分类号： H01L29/0847 ,  H01L27/088 ,  H01L29/0692 ,  H01L29/7835

    摘要： In a semiconductor device comprising a plurality of planar high-voltage insulated-gate field-effect transistors in which offset regions are provided in portions of the semiconductor substrate near the junctions of the adjacent drain regions and near the substrate surface, low impurity concentration offset regions are formed in the semiconductor substrate in such a manner that each low impurity concentration offset region is coupled the source region and is located between the drain regions of the field-effect transistors adjacent to each other and near the semiconductor surface, whereby reduction of the "on resistance" is achieved without affecting the FET sustaining voltage.

    Method of manufacturing an integrated CMOS of ordinary logic circuit and of high voltage MOS circuit
    35.
    发明授权
    Method of manufacturing an integrated CMOS of ordinary logic circuit and of high voltage MOS circuit 失效
    制造普通逻辑电路和高压MOS电路的集成CMOS的方法

    公开(公告)号：US4818719A

    公开(公告)日：1989-04-04

    申请号：US74059

    申请日：1987-07-16

    申请人： Ching-Fa Yeh ,  Yasunao Misawa ,  Yuji Yatsuda

    发明人： Ching-Fa Yeh ,  Yasunao Misawa ,  Yuji Yatsuda

    IPC分类号： H01L27/08 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/78 ,  H01L21/265

    CPC分类号： H01L21/8238 ,  H01L27/088

    摘要： A method of manufacturing a semiconductor device having a high voltage CMOS unit for an ordinary logic operation and a MOS unit which are provided in a single semiconductor substrate of a first conduction type. The method includes the steps of performing an element region making process for making a well of a second conduction type in the substrate, performing a process for providing field-effect transistors having channels of mutually different conduction types in the substrate and the well, and then performing a process for providing electrode wiring layers. Finally, a process is performed for providing a first impurity region having a particular conduction type and serving as a channel stopper of the CMOS unit and a second impurity region having the conduction type of the first impurity region and serving as an offset low-resistance layer of the high voltage MOS unit.

    摘要翻译： 一种制造具有用于普通逻辑运算的高电压CMOS单元和设置在第一导电类型的单个半导体衬底中的MOS单元的半导体器件的方法。 该方法包括以下步骤：在衬底中进行用于制造第二导电类型的阱的元件区域制造工艺，在衬底和阱中执行提供具有相互不同导电类型的沟道的场效应晶体管的工艺，然后 执行用于提供电极布线层的工艺。 最后，进行用于提供具有特定导电类型并用作CMOS单元的沟道阻挡的第一杂质区和具有第一杂质区的导电类型并用作偏移低电阻层的第二杂质区 的高压MOS单元。

    Defect-remediable semiconductor integrated circuit memory and spare substitution method in the same
    36.
    发明授权
    Defect-remediable semiconductor integrated circuit memory and spare substitution method in the same 失效
    缺陷补救半导体集成电路存储器和备用替代方法相同

    公开(公告)号：US4514830A

    公开(公告)日：1985-04-30

    申请号：US344974

    申请日：1982-02-02

    申请人： Takaaki Hagiwara ,  Masatada Horiuchi ,  Ryuji Kondo ,  Yuji Yatsuda ,  Shinichi Minami

    发明人： Takaaki Hagiwara ,  Masatada Horiuchi ,  Ryuji Kondo ,  Yuji Yatsuda ,  Shinichi Minami

    IPC分类号： H01L27/112 ,  G11C29/00 ,  G11C29/04 ,  H01L21/8246 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

    CPC分类号： G11C29/789

    摘要： An LSI memory comprises a memory array including usual memory cells arranged in a matrix form, usual address transistors for selecting usual lines connected to the columns or rows of the memory array, address lines for controlling the usual address transistors, spare memory cells provided in the memory array, a spare line connected to the spare memory cells, spare address transistors connected between the address lines and the spare lines, and nonvolatile memory elements connected between the sources of the spare address transistors and the ground. By putting any one of the nonvolatile memory elements into the written state, any one of the spare address transistors are conditioned into an active state so that the spare line can be substituted for a defective usual line.

    摘要翻译： LSI存储器包括存储器阵列，其包括以矩阵形式布置的常规存储器单元，用于选择连接到存储器阵列的列或行的常用线的常用地址晶体管，用于控制通常地址晶体管的地址线，设置在存储器阵列中的备用存储器单元 存储器阵列，连接到备用存储器单元的备用线路，连接在地址线和备用线路之间的备用地址晶体管，以及连接在备用地址晶体管的源极和地之间的非易失性存储器元件。 通过将非易失性存储器元件中的任何一个置于写入状态，任何一个备用地址晶体管被调节成活动状态，使得备用线可以代替缺陷通常的线。

    Nonvolatile MNOS semiconductor memory
    37.
    发明授权
    Nonvolatile MNOS semiconductor memory 失效
    非易失性MNOS半导体存储器

    公开(公告)号：US4460980A

    公开(公告)日：1984-07-17

    申请号：US193124

    申请日：1980-10-02

    申请人： Takaaki Hagiwara ,  Yokichi Itoh ,  Ryuji Kondo ,  Yuji Yatsuda ,  Shinichi Minami

    发明人： Takaaki Hagiwara ,  Yokichi Itoh ,  Ryuji Kondo ,  Yuji Yatsuda ,  Shinichi Minami

    IPC分类号： G11C17/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/417 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40 ,  H01L27/02 ,  H01L29/34 ,  H01L29/78

    CPC分类号： H01L27/105 ,  G11C16/0466 ,  H01L29/792 ,  Y10S257/903

    摘要： A semiconductor nonvolatile memory wherein a unit cell is constructed of a series connection consisting of an MNOS (metal--silicon nitride--silicon dioxide--semiconductor) transistor whose gate electrode is made of polycrystalline silicon and an MOS (metal--silicon dioxide--semiconductor) transistor whose gate electrode is also made of polycrystalline silicon, such unit cells being arrayed in the form of a matrix, and wherein the gate electrode of the MOS transistor is used as a reading word line, the gate electrode of the MNOS transistor is used as a writing word line, and a terminal of either of the MNOS transistor and the MOS transistor connected in series and constituting the unit cell is used as a data line.

    摘要翻译： 一种半导体非易失性存储器，其中单元由由栅电极由多晶硅制成的MNOS（金属 - 氮化硅 - 二氧化硅 - 半导体）晶体管和MOS（金属 - 二氧化硅 - 半导体）晶体管）构成的串联连接构成， 其栅极也由多晶硅制成，这样的单电池以矩阵的形式排列，其中MOS晶体管的栅极用作读取字线，MNOS晶体管的栅电极用作 写入字线，并且串联连接并构成单元的MNOS晶体管和MOS晶体管中的任一个的端子被用作数据线。

    Nonvolatile semiconductor memory
    40.
    发明授权
    Nonvolatile semiconductor memory 失效
    非易失性半导体存储器

    公开(公告)号：US4654828A

    公开(公告)日：1987-03-31

    申请号：US787021

    申请日：1985-10-15

    申请人： Takaaki Hagiwara ,  Yokichi Itoh ,  Ryuji Kondo ,  Yuji Yatsuda ,  Shinichi Minami

    发明人： Takaaki Hagiwara ,  Yokichi Itoh ,  Ryuji Kondo ,  Yuji Yatsuda ,  Shinichi Minami

    IPC分类号： G11C17/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/417 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40 ,  H01L27/02 ,  H01L29/34 ,  H01L29/78

    CPC分类号： H01L27/105 ,  G11C16/0466 ,  H01L29/792 ,  Y10S257/903

    摘要： A semiconductor nonvolatile memory wherein a unit cell is constructed of a series connection consisting of an MNOS (metal-silicon nitride-silicon dioxide-semiconductor) transistor whose gate electrode is made of polycrystalline silicon and an MOS (metal-silicon dioxide-semiconductor) transistor whose gate electrode is also made of polycrystalline silicon, such unit cells being arrayed in the form of a matrix, and wherein the gate electrode of the MOS transistor is used as a reading word line, the gate electrode of the MNOS transistor is used as a writing word line, and a terminal of either of the MNOS transistor and the MOS transistor connected in series and constituting the unit cell is used as a data line.

    摘要翻译： 一种半导体非易失性存储器，其中单元由由栅电极由多晶硅制成的MNOS（金属 - 氮化硅 - 二氧化硅 - 半导体）晶体管和MOS（金属 - 二氧化硅 - 半导体）晶体管）构成的串联连接构成， 其栅极也由多晶硅制成，这样的单电池以矩阵的形式排列，其中MOS晶体管的栅极用作读取字线，MNOS晶体管的栅电极用作 写入字线，并且串联连接并构成单元的MNOS晶体管和MOS晶体管中的任一个的端子被用作数据线。