公开(公告)号：US06653203B1

公开(公告)日：2003-11-25

申请号：US10154285

申请日：2002-05-23

申请人： Tsung-Hsun Huang ,  Yeur-Luen Tu ,  Chung Yi Yu

发明人： Tsung-Hsun Huang ,  Yeur-Luen Tu ,  Chung Yi Yu

IPC分类号： H01L2176

CPC分类号： H01L21/76224 ,  H01L21/76232

摘要： A multi-step HDP deposition and sputtering process for void-free filling of high aspect ratio trenches and for trenches having stepped cross-sectional profiles. The method is particularly applicable to filling trenches formed in triply layered substrates comprising a silicon layer, an oxide layer and a nitride layer, wherein the nitride layer has been pulled back from the edge of the trench opening and forms a step. The method allows the void-free filling of such a trench without damaging the nitride layer in the process. Briefly, the essence of the method is the formation of deposited layers on the sidewalls of the trench wherein the first layer is deposited with a high deposition to sputtering ratio (D/S>10) and low bias power to form a thin layer, with no overhang, that is capable of protecting the nitride layer during subsequent deposition and sputtering steps. A subsequent in-situ sputtering step at a lower D/S ratio using oxygen as the sputtering gas maintains a wide trench opening which then allows the complete filling to proceed using argon as the sputtering gas for increased throughput.

摘要翻译： 用于无高度填充高纵横比沟槽和具有阶梯形截面轮廓的沟槽的多步HDP沉积和溅射工艺。 该方法特别适用于填充形成在包括硅层，氧化物层和氮化物层的三层分层衬底中的沟槽，其中氮化物层已从沟槽开口的边缘拉回并形成一个步骤。 该方法允许这种沟槽的无空隙填充而不损害该过程中的氮化物层。 简而言之，该方法的本质是在沟槽的侧壁上形成沉积层，其中第一层以高沉积至溅射比（D / S> 10）沉积并具有低偏压功率以形成薄层，其中 没有悬垂，在后续沉积和溅射步骤中能够保护氮化物层。 使用氧作为溅射气体的较低D / S比率的随后的原位溅射步骤保持宽的沟槽开口，然后允许使用氩气作为溅射气体进行完全填充以提高生产量。

公开(公告)号：US06528366B1

公开(公告)日：2003-03-04

申请号：US09839964

申请日：2001-04-23

申请人： Yeur-Luen Tu ,  Dah Lin ,  Min-Hwa Chi

发明人： Yeur-Luen Tu ,  Dah Lin ,  Min-Hwa Chi

IPC分类号： H01L218242

CPC分类号： H01L28/87 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/91

摘要： Methods for fabricating a vertical metal-insulator-metal (MIM) capacitor are described. The capacitor can be fabricated at any level of metal interconnect, depending upon the desired depth of the capacitor. No global topology variations occur at any interconnect level in these methods. The entire process temperature is limited to be low enough, less than about 450° C., so that the back-end metal interconnect is not degraded or damaged. In one method, the deep capacitor cavity can be formed by etching back-end oxide (i.e. intermetal dielectric) from near the top level of metal interconnect until reaching the via-plug at several lower metal interconnect levels. In another method, metal lines and tungsten plugs are formed in both the logic and memory areas. Then, a selective wet metal etching is performed to remove the stacked tungsten plugs and metal lines for the formation of the capacitor cavity. After the capacitor cavity is formed by either method, the sidewall of the deep cavity is coated sequentially with a conformal conducting film as the bottom electrode and a high-k dielectric, and then filled with a conducting material to form the top electrode.

摘要翻译： 描述了用于制造垂直金属 - 绝缘体 - 金属（MIM）电容器的方法。 根据电容器的期望深度，可以在任何金属互连级别制造电容器。 在这些方法中，任何互连级别都不会发生全局拓扑变化。 整个工艺温度被限制为足够低，小于约450℃，使得后端金属互连不会降解或损坏。 在一种方法中，深电容器腔可以通过从靠近金属互连顶层的后端蚀刻后端氧化物（即金属间电介质）形成，直到在几个较低的金属互连级别到达通孔。 在另一种方法中，在逻辑区和存储区都形成金属线和钨插塞。 然后，进行选择性湿式金属蚀刻以去除用于形成电容器腔的堆叠的钨插塞和金属线。 在通过任一种方法形成电容器腔之后，依次用适形导电膜作为底部电极和高k电介质涂覆深腔的侧壁，然后填充导电材料以形成顶部电极。

公开(公告)号：US06187486B1

公开(公告)日：2001-02-13

申请号：US09250766

申请日：1999-02-16

申请人： Jun-Cheng Lai ,  Yeur-Luen Tu ,  Chine-Gie Lou

发明人： Jun-Cheng Lai ,  Yeur-Luen Tu ,  Chine-Gie Lou

IPC分类号： G03F900

CPC分类号： G03F7/70466 ,  G03F7/2022 ,  G03F7/203

摘要： A multi-exposure process. By performing the multi-exposure process, the size of the line width can be enlarged or shrunk by the precondition of the fixed pitch. Moreover, the line width can be shrunk to a level even smaller than the resolving power of the stepper or the scanner. Additionally, by using the invention, the exposure energy, the exposure time and the exposure DOF can be fixed while the exposure process is performed. Therefore, the process window is increased and the yield is enhanced. Furthermore, the processing sequence according to the invention is simpler than the conventional photolithography processing sequence, so that the throughput can be increased.

摘要翻译： 多曝光过程。 通过进行多次曝光处理，可以通过固定间距的前提来扩大或缩小线宽的尺寸。 此外，线宽可以缩小到甚至小于步进器或扫描仪的分辨率的水平。 此外，通过使用本发明，可以在执行曝光处理时固定曝光能量，曝光时间和曝光DOF。 因此，处理窗口增加，产量提高。 此外，根据本发明的处理顺序比常规的光刻处理顺序更简单，从而可以提高吞吐量。

公开(公告)号：US6165867A

公开(公告)日：2000-12-26

申请号：US246919

申请日：1999-02-09

申请人： Yeur-Luen Tu ,  Cheng-Yuan Hsu ,  Cheng-Yuan Chang

发明人： Yeur-Luen Tu ,  Cheng-Yuan Hsu ,  Cheng-Yuan Chang

IPC分类号： H01L21/768 ,  H01L21/8242 ,  H01L21/20

CPC分类号： H01L27/10894 ,  H01L21/76802 ,  H01L21/76829

摘要： The present invention provides a method for reducing aspect ratio of DRAM peripheral contact so as to achieving a good contact etching and metal deposition by utilizing conventional equipment. Besides, the present invention provides a stop layer formed by a nitride layer to reduce the volcano effect resulted from the misalignment between stacked contacts. Furthermore, the present invention is capable of etching poly layer and oxide layer in a single step, whereby the height of the peripheral contact is substantially the same as, or lower than, the contact of the storage node of a capacitor. Therefore, the aspect ratio of DRAM peripheral contact can be reduced.

摘要翻译： 本发明提供一种降低DRAM周边接触的纵横比的方法，以便通过利用常规设备实现良好的接触蚀刻和金属沉积。 此外，本发明提供了由氮化物层形成的停止层，以减少由于堆叠的触点之间的未对准而导致的火山效应。 此外，本发明能够在一个步骤中蚀刻多层和氧化物层，由此周边接触的高度与电容器的存储节点的接触基本相同或低于接触。 因此，可以减小DRAM周边接触的纵横比。

公开(公告)号：US06143664A

公开(公告)日：2000-11-07

申请号：US928205

申请日：1997-09-12

申请人： Liang-Gi Yao ,  Chung-Ju Lee ,  Yue-Feng Chen ,  Wei-Ray Lin ,  Yeur-Luen Tu

发明人： Liang-Gi Yao ,  Chung-Ju Lee ,  Yue-Feng Chen ,  Wei-Ray Lin ,  Yeur-Luen Tu

IPC分类号： H01L21/768 ,  H01L21/00

CPC分类号： H01L21/76819

摘要： A method of planarizing a structure having an interpoly layer is disclosed. The method includes forming an undoped silica glass layer on at least a polysilicon region formed on a semiconductor substrate. Next, a spin-on-glass layer is formed over the undoped silica glass layer. Finally, the spin-on-glass layer is etched back, thereby planarizing the structure having the interpoly layer.

摘要翻译： 公开了一种平面化具有多晶硅层的结构的方法。 该方法包括在至少形成在半导体衬底上的多晶硅区域上形成未掺杂的二氧化硅玻璃层。 接下来，在未掺杂的二氧化硅玻璃层上形成旋涂玻璃层。 最后，将旋涂玻璃层回蚀刻，从而使具有多晶硅层的结构平坦化。

公开(公告)号：US6136716A

公开(公告)日：2000-10-24

申请号：US189067

申请日：1998-11-09

申请人： Yeur-Luen Tu

发明人： Yeur-Luen Tu

IPC分类号： H01L21/02 ,  H01L21/60 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/311

CPC分类号： H01L27/10888 ,  H01L21/76897 ,  H01L28/60 ,  H01L27/10814 ,  H01L28/91

摘要： A method for manufacturing a self-aligned stacked storage node DRAM cell on a substrate for a capacitor over bit line (COB) process is disclosed. The method comprises the steps of: forming a first planarized dielectric layer onto the substrate; forming a first planarized barrier layer onto the first dielectric layer; patterning and etching the first barrier layer until the first dielectric layer is reached to form a bit line contact and a storage node contact; forming first sidewall barrier spacers on the sides of the first barrier layer; etching the first dielectric layer until the substrate is reached to form a bit line contact opening and a storage node contact opening; depositing a first conducting layer into and above the bit line contact opening and the storage node contact opening and above the first barrier layer and the first sidewall spacers; depositing a second conducting layer onto the first conducting layer; depositing a cap barrier layer atop the second conducting layer; patterning and etching the first conducting layer, the second conducting layer, and the cap barrier layer to form an intermediate structure above the bit line contact opening and a plug in the storage node opening; forming second sidewall barrier spacers on the sides of the intermediate structure; forming a second dielectric layer onto exposed portions of the first and the second sidewall barrier spacers, the plug and the cap barrier layer; patterning and etching the second dielectric layer leaving a remaining portion only on the intermediate structure; forming a third conducting layer onto exposed portions of the plug, the first and the second side wall barrier spacers, the cap barrier layer, and the remaining portion of the third dielectric layer; and removing the third conducting layer atop the second dielectric layer.

摘要翻译： 公开了一种用于通过位线（COB）工艺在电容器用基板上制造自对准堆叠存储节点DRAM单元的方法。 该方法包括以下步骤：在衬底上形成第一平坦化介电层; 在所述第一介电层上形成第一平坦化阻挡层; 图案化和蚀刻第一阻挡层直到达到第一介电层以形成位线接触和存储节点接触; 在所述第一阻挡层的侧面上形成第一侧壁阻挡间隔物; 蚀刻第一介电层，直到达到基板以形成位线接触开口和存储节点接触开口; 在所述位线接触开口和所述存储节点接触开口中以及所述第一阻挡层和所述第一侧壁间隔物之上沉积第一导电层; 在所述第一导电层上沉积第二导电层; 在所述第二导电层顶上沉积帽阻挡层; 图案化和蚀刻第一导电层，第二导电层和帽阻挡层，以形成位线接触开口之上的中间结构和存储节点开口中的插塞; 在所述中间结构的侧面上形成第二侧壁阻挡间隔物; 在所述第一和第二侧壁阻挡间隔物，所述插塞和所述帽阻挡层的暴露部分上形成第二电介质层; 图案化和蚀刻第二介电层，留下仅在中间结构上的剩余部分; 在所述插头的暴露部分，所述第一和第二侧壁阻挡间隔物，所述帽阻挡层和所述第三介电层的剩余部分上形成第三导电层; 以及在所述第二介电层顶部移除所述第三导电层。

公开(公告)号：US6117748A

公开(公告)日：2000-09-12

申请号：US60771

申请日：1998-04-15

申请人： Chine-Gie Lou ,  Yeur-Luen Tu ,  Ko-Hsing Chang

发明人： Chine-Gie Lou ,  Yeur-Luen Tu ,  Ko-Hsing Chang

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： A thin silicon dioxide layer is formed on a substrate to act as a pad oxide layer. Subsequently, a Si.sub.3 N.sub.4 or BN layer is deposited on the pad oxide layer. An in situ doped polysilicon layer is deposited on the Si.sub.3 N.sub.4 or BN layer. A trench is formed in the substrate. An oxide liner is formed along the walls of the trench and on the surface of the in situ doped polysilicon layer. A CVD oxide layer is formed on the oxide liner and refilled into the trench. A two-step chemical mechanical polishing (CMP) removes the layers to the surface of the Si.sub.3 N.sub.4 or BN layer. The first step of the two-step CMP is an oxide slurry CMP that is stopped at about 100 to 500 angstroms from the in situ doped polysilicon layer. The second step of the two-step CMP is a poly slurry CMP that is controlled to stop at the surface of the Si.sub.3 N.sub.4 or BN layer.

摘要翻译： 在基板上形成薄的二氧化硅层，作为衬垫氧化物层。 随后，在衬垫氧化物层上沉积Si 3 N 4或BN层。 在Si 3 N 4或BN层上沉积原位掺杂多晶硅层。 在衬底中形成沟槽。 沿着沟槽的壁和原位掺杂的多晶硅层的表面上形成氧化物衬垫。 在氧化物衬垫上形成CVD氧化层，并重新填充到沟槽中。 两步化学机械抛光（CMP）去除层到Si3N4或BN层的表面。 两步CMP的第一步是从原位掺杂的多晶硅层停止在约100至500埃处的氧化物浆料CMP。 两步CMP的第二步是控制在Si3N4或BN层表面停止的聚浆料CMP。

公开(公告)号：US5943599A

公开(公告)日：1999-08-24

申请号：US920133

申请日：1997-08-27

申请人： Liang-Gi Yao ,  Yeur-Luen Tu ,  Sen-Huan Huang ,  Kwong-Jr Tsai ,  Meng-Jaw Cherng

发明人： Liang-Gi Yao ,  Yeur-Luen Tu ,  Sen-Huan Huang ,  Kwong-Jr Tsai ,  Meng-Jaw Cherng

IPC分类号： H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/4763

CPC分类号： H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31612 ,  H01L21/3185 ,  H01L21/3145 ,  Y10S438/958

摘要： A metal layer (24) is formed on an isolation layer (22) to act as interconnections. Subsequently, a thin liner layer (26) is optionally formed along the surface of the metal layer (24) to serve as a buffer layer. An undoped silicate glass (USG) layer (28) is deposited on the liner layer (26). The USG layer (28) is formed using ozone and tetraethylorthosilicate (TEOS) as a source at a temperature of approximately 380 to 420.degree. C. Oxygen gas is used as a carrier for the ozone. The flow rate of the oxygen gas is approximately 4000 to 6000 sccm. Helium gas is used as a carrier for the TEOS. The flow rate of the helium is approximately 3000 to 5000 sccm. A silicon nitride layer (30) is deposited on the USG layer (28) using plasma enhanced chemical vapor deposition (PECVD). The silicon nitride layer (30) serves as a main passivation layer. The thickness of the silicon nitride layer (30) is approximately 3000 to 7000 angstroms.

摘要翻译： 金属层（24）形成在隔离层（22）上以用作互连。 随后，沿着金属层（24）的表面可选地形成薄衬层（26），用作缓冲层。 未掺杂的硅酸盐玻璃（USG）层（28）沉积在衬层（26）上。 USG层（28）使用臭氧和原硅酸四乙酯（TEOS）作为源，在约380至420℃的温度下形成。氧气用作臭氧的载体。 氧气的流量约为4000〜6000sccm。 氦气用作TEOS的载体。 氦气的流量约为3000〜5000sccm。 使用等离子体增强化学气相沉积（PECVD）在USG层（28）上沉积氮化硅层（30）。 氮化硅层（30）用作主钝化层。 氮化硅层（30）的厚度约为3000至7000埃。

公开(公告)号：US5916823A

公开(公告)日：1999-06-29

申请号：US170859

申请日：1998-10-13

申请人： Chine-Gie Lou ,  Yeur-Luen Tu

发明人： Chine-Gie Lou ,  Yeur-Luen Tu

IPC分类号： H01L21/768 ,  H01L21/32 ,  C25D11/04

CPC分类号： H01L21/76831 ,  H01L21/7681 ,  H01L21/76832

摘要： A method for forming a dual damascene structure on a substrate is disclosed. The method comprises the steps of: forming a liner oxide layer onto the substrate; forming a first low k dielectric layer atop the liner oxide layer; forming a cap oxide layer atop the first low k dielectric layer; forming a first nitride layer atop the cap oxide layer; patterning and etching the first nitride layer to form a contact opening; forming a second low k dielectric layer into the contact opening and atop the first nitride layer; forming a second nitride layer atop the second low k dielectric layer; forming a photoresist layer atop the second nitride layer; patterning and developing the photoresist layer to expose a trench opening, wherein the trench opening is of different dimension than the contact opening; forming a dual damascene opening by etching the second nitride layer and the second low k dielectric layer, using the photoresist layer as a mask, and by etching the cap oxide layer, the first low k dielectric layer and the liner oxide layer, using the first nitride layer as a mask; stripping the photoresist layer; forming oxide sidewall spacers into the dual damascene opening; and depositing a conductive layer into the dual damascene opening.

摘要翻译： 公开了一种在衬底上形成双镶嵌结构的方法。 该方法包括以下步骤：在衬底上形成衬垫氧化物层; 在衬垫氧化物层的上方形成第一低k电介质层; 在第一低k电介质层的顶部形成帽氧化物层; 在所述盖氧化物层顶上形成第一氮化物层; 图案化和蚀刻第一氮化物层以形成接触开口; 在所述接触开口中和所述第一氮化物层的顶上形成第二低k电介质层; 在所述第二低k电介质层的顶部形成第二氮化物层; 在所述第二氮化物层的顶部形成光致抗蚀剂层; 图案化和显影光致抗蚀剂层以露出沟槽开口，其中沟槽开口的尺寸与接触开口不同; 通过使用所述光致抗蚀剂层作为掩模蚀刻所述第二氮化物层和所述第二低k电介质层，并且通过使用所述第一低k介电层和所述衬底氧化物层蚀刻所述第一低k电介质层和所述衬里氧化物层来形成双镶嵌开口 氮化物层作为掩模; 剥离光致抗蚀剂层; 在所述双镶嵌开口中形成氧化物侧壁间隔物; 以及将导电层沉积到双镶嵌开口中。

公开(公告)号：US5851603A

公开(公告)日：1998-12-22

申请号：US891910

申请日：1997-07-14

申请人： Kwong-Jr Tsai ,  Shiang-Peng Cheng ,  Yeur-Luen Tu ,  Ing-Ruey Liaw

发明人： Kwong-Jr Tsai ,  Shiang-Peng Cheng ,  Yeur-Luen Tu ,  Ing-Ruey Liaw

IPC分类号： H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/532 ,  B05D3/06

CPC分类号： H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/3145 ,  H01L21/31612 ,  H01L21/3185 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L21/76837 ,  H01L2924/0002 ,  Y10S438/938 ,  Y10T428/24917

摘要： A method was achieved for forming a multilayer passivation layer comprised of a silicon oxide/silicon nitride/silicon oxide/silicon nitride by depositing the layers consecutively in a single PECVD system. The method consists of depositing a first SiO.sub.2 layer that serves as a stress-release layer, a thin Si.sub.3 N.sub.4 layer that serves as a buffer layer that minimizes cracking and as a passivation layer that prevents mobile alkaline ion penetration, a thin second SiO.sub.2 layer to fill and seal any remaining cracks and pinholes in the first Si.sub.3 N.sub.4 layer, and a main Si.sub.3 N.sub.4 passivation layer that prevents water and/or other corrosive chemicals from attacking the metal. Since this multilayer passivation layer can be deposited essentially pinhole-free to a thickness that is less than the prior art's passivation layer of 8000 Angstroms needed to prevent pinholes, it can be used on 0.38 to 0.25 um DRAM technology, which eliminates voids that could otherwise trap photoresist which can later cause corrosion of the metal lines.

摘要翻译： 通过在单个PECVD系统中连续沉积层来形成由氧化硅/氮化硅/氧化硅/氮化硅组成的多层钝化层的方法。 该方法包括沉积用作应力释放层的第一SiO 2层，用作最小化裂纹的缓冲层的薄Si 3 N 4层，以及防止移动碱性离子渗透的钝化层，稀的第二SiO 2层填充 并且密封第一Si 3 N 4层中的任何剩余的裂纹和针孔，以及防止水和/或其它腐蚀性化学物质侵蚀金属的主要Si 3 N 4钝化层。 由于这种多层钝化层可以基本上无针孔地沉积到比现有技术的防止针孔所需的8000埃的钝化层的厚度，所以它可以用于0.38到0.25微米的DRAM技术，这消除了否则的空隙 陷阱光致抗蚀剂可以后来导致金属线的腐蚀。