METHOD TO PROVIDE A TIME-OF-FLIGHT ESTIMATE
    32.
    发明公开

    公开(公告)号:US20240201351A1

    公开(公告)日:2024-06-20

    申请号:US18532939

    申请日:2023-12-07

    IPC分类号: G01S7/52

    CPC分类号: G01S7/52025

    摘要: Method to provide a TOF estimate by a TOF device. The method comprises: generating an electric echo signal indicative of an ultrasonic echo signal returned by a target body by the ultrasonic source signal; determining an envelope signal indicative of an envelope of the electric echo signal; generating a first TOF estimate by processing the electric echo signal; determining an envelope signal portion of the envelope signal based on a non-PSOA hyperparameter; and generating a second TOF estimate by processing the envelope signal portion through PSOA, the second TOF estimate having a measurement accuracy value greater than that of the first TOF estimate. PSOA is optimized based on a PSOA hyperparameter set. The non-PSOA hyperparameter and the PSOA hyperparameter set are selected among a plurality of choices based on the first TOF estimate, so as to obtain the second TOF estimate which has greater accuracy than the first TOF estimate.

    PROCESS FOR MANUFACTURING A MICRO-ELECTRO-MECHANICAL DEVICE, AND MEMS DEVICE

    公开(公告)号:US20240199408A1

    公开(公告)日:2024-06-20

    申请号:US18590533

    申请日:2024-02-28

    IPC分类号: B81B3/00 B81C1/00

    摘要: A process for manufacturing a MEMS device includes forming a first structural layer of a first thickness on a substrate. First trenches are formed through the first structural layer, and masking regions separated by first openings are formed on the first structural layer. A second structural layer of a second thickness is formed on the first structural layer in direct contact with the first structural layer at the first openings and forms, together with the first structural layer, thick structural regions having a third thickness equal to the sum of the first and the second thicknesses. A plurality of second trenches are formed through the second structural layer, over the masking regions, and third trenches are formed through the first and the second structural layers by removing selective portions of the thick structural regions.

    Control loop and efficiency enhancement for DC-DC converters

    公开(公告)号:US12015346B2

    公开(公告)日:2024-06-18

    申请号:US17565674

    申请日:2021-12-30

    IPC分类号: H02M3/158 H02M1/00 H02M1/08

    CPC分类号: H02M3/158 H02M1/0025 H02M1/08

    摘要: A DC-DC boost converter includes an inductor coupled between an input voltage and an input node, a diode coupled between the input node and an output node, and an output capacitor coupled between the output node and ground such that an output voltage is formed across the output capacitor. A switch selectively couples the input node to ground in response to a drive signal. Control loop circuitry includes an error amplifier to generate an analog error voltage based upon a comparison of a feedback voltage to a reference voltage, the feedback voltage being indicative of the output voltage, a quantizer to quantize the analog error voltage to produce a digital error signal, and a drive voltage generation circuit to generate the drive signal as having a duty cycle based upon the digital error signal.

    Hardware accelerator device, corresponding system and method of operation

    公开(公告)号:US11996158B2

    公开(公告)日:2024-05-28

    申请号:US18349565

    申请日:2023-07-10

    摘要: A device includes a set of processing circuits arranged in subsets, a set of data memory banks coupled to a memory controller, a control unit, and an interconnect network. The processing circuits are configurable to read first input data from the data memory banks via the interconnect network and the memory controller, process the first input data to produce output data, and write the output data into the data memory banks via the interconnect network and the memory controller. The hardware accelerator device includes a set of configurable lock-step control units which interface the processing circuits to the interconnect network. Each configurable lock-step control unit is coupled to a subset of processing circuits and is selectively activatable to operate in a first operation mode, or in a second operation mode.