公开(公告)号：US09841446B1

公开(公告)日：2017-12-12

申请号：US15180814

申请日：2016-06-13

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Lukas Vaculik ,  Jan Tomecek

IPC: G01R13/34 ,  G01R13/02 ,  G01R21/133 ,  H03M1/50 ,  G01R19/25 ,  H03M1/12

CPC classification number: G01R19/2506 ,  G01R13/0272 ,  G01R13/34 ,  G01R13/345 ,  G01R19/0053 ,  G01R23/02 ,  H03M1/0656 ,  H03M1/12 ,  H03M1/1255

Abstract: A method, apparatus, and energy metering system obtains mains samples of a mains power line signal, performs non-white noise (NWN) filtering of the mains power line signal, obtains adjustable clock source samples of an adjustable clock signal of an adjustable clock oscillator, determines a difference based on the mains samples and the adjustable clock source samples, adjusts an adjustable clock source frequency of the adjustable clock oscillator based on the difference, and applies the adjustable clock source frequency to an analog to digital converter (ADC) to determine a conversion rate of the ADC.

公开(公告)号：US08823564B2

公开(公告)日：2014-09-02

申请号：US13882251

申请日：2012-12-27

Applicant: Asahi Kasei Microdevices Corporation

Inventor： Junya Nakanishi ,  Yutaka Nakanishi

IPC: H03M1/00 ,  G11C27/02 ,  H03M1/08 ,  H03M1/12 ,  H03M1/66

CPC classification number: G11C27/024 ,  G11C7/02 ,  G11C7/16 ,  G11C27/02 ,  G11C27/026 ,  H03M1/0656 ,  H03M1/0827 ,  H03M1/12 ,  H03M1/66

Abstract: A sampling circuit includes a continuous section which is a circuit for transmitting a continuous signal; a digital section for transmitting a signal which is sampled and quantized; and a sampling and holding section for transmitting a signal which is sampled but not quantized between the continuous section and the digital section. The sampling and holding section includes capacitors for accumulating charge generated by an input signal and plural switches for accumulating the charge in the capacitors. The plural switches receive plural clock signals having different operation timings and perform an ON/OFF operation in response to the supplied clock signals.

Abstract translation: 采样电路包括作为用于发送连续信号的电路的连续部分; 用于发送被采样和量化的信号的数字部分; 以及采样和保持部分，用于发送在连续部分和数字部分之间被采样但未量化的信号。 采样和保持部分包括用于累积由输入信号产生的电荷的电容器和用于在电容器中累积电荷的多个开关。 多个开关接收具有不同操作定时的多个时钟信号，并且响应于所提供的时钟信号执行ON / OFF操作。

公开(公告)号：US20140062741A1

公开(公告)日：2014-03-06

申请号：US13882251

申请日：2012-12-27

Applicant: ASAHI KASEI MICRODEVICES CORPORATION

Inventor： Junya Nakanishi ,  Yutaka Nakanishi

IPC: G11C27/02

CPC classification number: G11C27/024 ,  G11C7/02 ,  G11C7/16 ,  G11C27/02 ,  G11C27/026 ,  H03M1/0656 ,  H03M1/0827 ,  H03M1/12 ,  H03M1/66

Abstract: A sampling circuit includes a continuous section which is a circuit for transmitting a continuous signal; a digital section for transmitting a signal which is sampled and quantized; and a sampling and holding section for transmitting a signal which is sampled but not quantized between the continuous section and the digital section. The sampling and holding section includes capacitors for accumulating charge generated by an input signal and plural switches for accumulating the charge in the capacitors. The plural switches receive plural clock signals having different operation timings and perform an ON/OFF operation in response to the supplied clock signals.

Abstract translation: 采样电路包括作为用于发送连续信号的电路的连续部分; 用于发送被采样和量化的信号的数字部分; 以及采样和保持部分，用于发送在连续部分和数字部分之间被采样但未量化的信号。 采样和保持部分包括用于累积由输入信号产生的电荷的电容器和用于在电容器中累积电荷的多个开关。 多个开关接收具有不同操作定时的多个时钟信号，并且响应于所提供的时钟信号执行ON / OFF操作。

公开(公告)号：US08593315B2

公开(公告)日：2013-11-26

申请号：US13577845

申请日：2011-01-20

Applicant: Tomoyuki Yamase ,  Hidemi Noguchi

Inventor： Tomoyuki Yamase ,  Hidemi Noguchi

IPC: H03M1/06

CPC classification number: H03M1/0656 ,  H03M1/0678 ,  H03M1/0697 ,  H03M1/365

Abstract: An A/D conversion unit performs an A/D conversion operation twice during a hold period of an analog value. In a first conversion operation, the A/D conversion unit compares the analog value with a first reference voltage and outputs a comparison result as first converted data. In a second conversion operation, the A/D conversion unit compares the analog value with a second reference voltage and outputs a comparison result as second converted data. The second reference voltage is a voltage obtained by adding or subtracting a minimum resolution voltage to or from the first reference voltage. A digital processing unit averages errors of the first and second converted data by digital processing to detect an A/D conversion error, and feeds back a detection result to the A/D conversion unit as a control value to perform voltage control.

Abstract translation: A / D转换单元在模拟值的保持期间进行两次A / D转换操作。 在第一转换操作中，A / D转换单元将模拟值与第一参考电压进行比较，并输出比较结果作为第一转换数据。 在第二转换操作中，A / D转换单元将模拟值与第二参考电压进行比较，并将比较结果作为第二转换数据输出。 第二参考电压是通过对或从第一参考电压加或减最小分辨率电压而获得的电压。 数字处理单元通过数字处理对第一和第二转换数据的误差进行平均以检测A / D转换误差，并将检测结果反馈到A / D转换单元作为控制值，以执行电压控制。

公开(公告)号：US08059019B2

公开(公告)日：2011-11-15

申请号：US11684572

申请日：2007-03-09

Applicant: Arne Aas ,  Gunnar Gangstoe ,  Torgeir Fenheim

Inventor： Arne Aas ,  Gunnar Gangstoe ,  Torgeir Fenheim

IPC: H03M1/06

CPC classification number: G01R19/0092 ,  G01R19/2509 ,  H03M1/0607 ,  H03M1/0656 ,  H03M3/34 ,  H03M3/356

Abstract: A method and system utilized with an analog to digital converter is disclosed. The method and system comprise providing a first conversion on an input signal. In the first conversion, an offset error is added to the input signal to provide a first result. The method and system further includes providing a second conversion on the input signal. In the second conversion, an offset error is subtracted from the input signal to provide a second result. The first and second results are then combined to substantially remove the offset error. A system and method in accordance with the present invention compensates for the accumulated offset error over many samples, thereby achieving much higher accuracy in the offset error compensation.

Abstract translation: 公开了一种使用模数转换器的方法和系统。 该方法和系统包括在输入信号上提供第一转换。 在第一次转换中，偏移误差被添加到输入信号以提供第一结果。 该方法和系统还包括对输入信号提供第二转换。 在第二转换中，从输入信号中减去偏移误差以提供第二结果。 然后组合第一和第二结果以基本上去除偏移误差。 根据本发明的系统和方法补偿多个样本上的累积偏移误差，从而在偏移误差补偿中获得高得多的精度。

公开(公告)号：US07999715B2

公开(公告)日：2011-08-16

申请号：US12716815

申请日：2010-03-03

Applicant: Ryo Yamaki ,  Toshiyuki Yamagishi

Inventor： Ryo Yamaki ,  Toshiyuki Yamagishi

IPC: H03M1/12

CPC classification number: H03M1/0863 ,  H03M1/0656 ,  H03M1/0827 ,  H03M1/12

Abstract: An interference reduction device includes an analog to digital converter, a serial to parallel converter, a first FIR filter, a second FIR filters, a flip-flop, a decision unit, and a selector. The analog to digital converter performs A/D conversion. The serial to parallel converter performs a session of distribution processing in which a digital signal obtained by the A/D conversion. The first FIR outputs the signal after a filter operation at the desired output frequency. The second FIR filters each perform a filter operation, also each output the generated signals at the desired output frequency. The flip-flop samples the inputted digital signal. The decision unit decides which one of the FIR filters has the smallest influence of interference of the input digital signal. The selector outputs one of the signals outputted by the FIR filters.

Abstract translation: 干扰减少装置包括模数转换器，串并转换器，第一FIR滤波器，第二FIR滤波器，触发器，判定单元和选择器。 模数转换器执行A / D转换。 串行到并行转换器执行通过A / D转换获得的数字信号的分配处理会话。 第一个FIR在滤波器操作之后以期望的输出频率输出信号。 第二FIR滤波器各自执行滤波操作，并且每个都输出所需的输出频率上产生的信号。 触发器对输入的数字信号进行采样。 决定单元决定哪个FIR滤波器对输入数字信号的干扰影响最小。 选择器输出FIR滤波器输出的信号之一。

公开(公告)号：US07956787B2

公开(公告)日：2011-06-07

申请号：US12339751

申请日：2008-12-19

Applicant: Alan Westwick ,  Xiaoling Guo

Inventor： Alan Westwick ,  Xiaoling Guo

IPC: H03M1/12

CPC classification number: H03M1/0636 ,  H03M1/0643 ,  H03M1/0656 ,  H03M1/122 ,  H03M1/468 ,  H03M1/68 ,  H03M1/804

Abstract: A method for operating an N-bit SAR ADC as a greater than N-bit resolution SAR ADC includes the steps of taking a plurality of samples for each analog value being converted to a digital value by the SAR ADC. A portion of an LSB is added to all but one of the plurality of samples. The plurality of samples are then accumulated and output as a digital value. The digital value has a resolution greater than the N-bit resolution of the SAR ADC.

Abstract translation: 用于将N位SAR ADC操作为大于N位分辨率SAR ADC的方法包括以下步骤：对于通过SAR ADC将每个模拟值转换为数字值的多个样本。 LSB的一部分被添加到多个样本中的除一个之外的所有样本。 然后将多个样本累积并作为数字值输出。 数字值的分辨率大于SAR ADC的N位分辨率。

公开(公告)号：US20100295716A1

公开(公告)日：2010-11-25

申请号：US12716815

申请日：2010-03-03

Applicant: Ryo Yamaki ,  Toshiyuki Yamagishi

Inventor： Ryo Yamaki ,  Toshiyuki Yamagishi

IPC: H03M1/12

CPC classification number: H03M1/0863 ,  H03M1/0656 ,  H03M1/0827 ,  H03M1/12

Abstract: An interference reduction device includes an analog to digital converter, a serial to parallel converter, a first FIR filter, a second FIR filters, a flip-flop, a decision unit, and a selector. The analog to digital converter performs A/D conversion. The serial to parallel converter performs a session of distribution processing in which a digital signal obtained by the A/D conversion. The first FIR outputs the signal after a filer operation at the desired output frequency. The second FIR filters each perform a filter operation, also each output the generated signals at the desired output frequency. The flip-flop samples the inputted digital signal. The decision unit decides which one of the FIR filters has the smallest influence of interference of the input digital signal. The selector outputs one of the signals outputted by the FIR filters.

Abstract translation: 干扰减少装置包括模数转换器，串并转换器，第一FIR滤波器，第二FIR滤波器，触发器，判定单元和选择器。 模数转换器执行A / D转换。 串行到并行转换器执行通过A / D转换获得的数字信号的分配处理会话。 第一个FIR在所需的输出频率下在文件管理器操作之后输出信号。 第二FIR滤波器各自执行滤波操作，并且每个都输出所需的输出频率上产生的信号。 触发器对输入的数字信号进行采样。 决定单元决定哪个FIR滤波器对输入数字信号的干扰影响最小。 选择器输出FIR滤波器输出的信号之一。

公开(公告)号：US20100156684A1

公开(公告)日：2010-06-24

申请号：US12339751

申请日：2008-12-19

Applicant: ALAN WESTWICK ,  XIAOLING GUO

Inventor： ALAN WESTWICK ,  XIAOLING GUO

IPC: H03M1/20 ,  H03M1/12

CPC classification number: H03M1/0636 ,  H03M1/0643 ,  H03M1/0656 ,  H03M1/122 ,  H03M1/468 ,  H03M1/68 ,  H03M1/804

Abstract: A method for operating an N-bit SAR ADC as a greater than N-bit resolution SAR ADC includes the steps of taking a plurality of samples for each analog value being converted to a digital value by the SAR ADC. A portion of an LSB is added to all but one of the plurality of samples. The plurality of samples are then accumulated and output as a digital value. The digital value has a resolution greater than the N-bit resolution of the SAR ADC.

Abstract translation: 用于将N位SAR ADC操作为大于N位分辨率SAR ADC的方法包括以下步骤：对于通过SAR ADC将每个模拟值转换为数字值的多个样本。 LSB的一部分被添加到多个样本中的除一个之外的所有样本。 然后将多个样本累积并作为数字值输出。 数字值的分辨率大于SAR ADC的N位分辨率。

公开(公告)号：US20090140896A1

公开(公告)日：2009-06-04

申请号：US12275871

申请日：2008-11-21

Applicant: Pietro Mario Adduci ,  Edoardo Botti ,  Giovanni Gonano

Inventor： Pietro Mario Adduci ,  Edoardo Botti ,  Giovanni Gonano

IPC: H03M1/66

CPC classification number: H03M1/0656 ,  H03L7/0805 ,  H03L7/0995 ,  H03L7/18 ,  H03M1/66

Abstract: A process and apparatus for generating an output signal whose frequency varies according to a modulation scheme, the process including the steps of providing a dither generator for receiving a first input signal representative of a clock frequency and for generating, according to the modulation scheme, a dithered output signal representative of the first signal at a dithered frequency; providing a DSP for receiving the following input signals: the signal at the dithered frequency and a second signal representative of a clock frequency, the DSP adapted to generate a processed output signal representative of the maximum frequency of the second signal; wherein the modulation scheme has a periodic ultrasonic modulating wave.

Abstract translation: 一种用于产生其频率根据调制方案而变化的输出信号的处理和装置，所述处理包括以下步骤：提供用于接收表示时钟频率的第一输入信号的抖动发生器，并根据调制方案生成 以抖动​​频率表示第一信号的抖动输出信号; 提供用于接收以下输入信号的DSP：处于抖动频率的信号和表示时钟频率的第二信号，DSP适于产生表示第二信号的最大频率的经处理的输出信号; 其中调制方案具有周期性超声波调制波。