公开(公告)号：US07912118B2

公开(公告)日：2011-03-22

申请号：US11524275

申请日：2006-09-21

申请人： Xianbin Wang ,  Yiyan Wu ,  Benoit Ledoux ,  Sebastien Lafleche ,  Gilles Gagnon

发明人： Xianbin Wang ,  Yiyan Wu ,  Benoit Ledoux ,  Sebastien Lafleche ,  Gilles Gagnon

IPC分类号： H03K5/159

CPC分类号： H04L25/03006 ,  H04L25/0236 ,  H04L2025/03382 ,  H04L2025/0349 ,  H04L2025/03617

摘要： The invention provides a method and device for iterative hybrid time-frequency domain block equalization of signals received via a communication channel subject to multipath interference. The equalization method includes frequency-domain equalization of blocks of received signals in a forward path, and time-domain inter-block echo correction and intra-block cyclic echo addition in the feedback path. The invention can be used for equalizing signals transmitted without cyclic prefix and subjected to multi-path interference with long delay spread.

摘要翻译： 本发明提供一种用于经由经受多路径干扰的通信信道接收的信号的迭代混合时频域块均衡的方法和装置。 均衡方法包括在正向路径中的接收信号块的频域均衡，以及反馈路径中的时域块间回波校正和块内循环回波加法。 本发明可以用于均衡在没有循环前缀的情况下发送的信号，并且经受具有长延迟扩展的多径干扰。

公开(公告)号：US20100329326A1

公开(公告)日：2010-12-30

申请号：US12495547

申请日：2009-06-30

申请人： Pervez M. Aziz ,  Adam B. Healey ,  Amaresh Malipatil ,  Lizhi Zhong

发明人： Pervez M. Aziz ,  Adam B. Healey ,  Amaresh Malipatil ,  Lizhi Zhong

IPC分类号： H04L27/01

CPC分类号： H04L25/03057 ,  H04L25/14 ,  H04L2025/03503 ,  H04L2025/03535 ,  H04L2025/03617

摘要： Methods and apparatus are provided for decision-feedback equalization with an oversampled phase detector. A method is provided for detecting data in a receiver employing decision-feedback equalization. A received signal is sampled using a data clock and a transition clock to generate a data sample signal and a transition sample signal. A DFE correction is obtained for each of the data sample and transition sample signals to generate DFE detected data and DFE transition data. One or more coefficients used for the DFE correction for the transition sample signals are adapted using the DFE transition data.

摘要翻译： 提供了使用过采样相位检测器进行判决反馈均衡的方法和装置。 提供一种用于使用判决反馈均衡来检测接收机中的数据的方法。 使用数据时钟和转换时钟对接收到的信号进行采样，以生成数据采样信号和转换采样信号。 为每个数据采样和转换采样信号获得DFE校正，以产生DFE检测数据和DFE转换数据。 用于转换采样信号的DFE校正的一个或多个系数使用DFE转换数据进行调整。

公开(公告)号：US20100322339A1

公开(公告)日：2010-12-23

申请号：US12747111

申请日：2008-12-09

申请人： Luc Fety ,  Philippe Mege ,  Laurent Martinod

发明人： Luc Fety ,  Philippe Mege ,  Laurent Martinod

IPC分类号： H04B15/00

CPC分类号： H04L25/03159 ,  H04B1/123 ,  H04B7/0851 ,  H04L1/06 ,  H04L2025/03414 ,  H04L2025/03617

摘要： To reduce interferences in signals received by a receiver through a propagation channel, each including symbols distributed according to frequency and time dimensions and corresponding to a common emitted signal, the receiver weights an estimate of the emitted signal and the received signals by weighting vectors evolving in vector subspaces representing time variations and frequency variations of the channels for propagating the signals between an emitter and the receiver. These vector subspaces are defined by matrices, some columns of which are suppressed as a function of frequency and time constraints of the channel. The receiver minimizes a function of the difference between the sum of weighted received signals and the weighted estimate of the emitted signal in order to estimate the emitted signal as a function of the weighting vectors and the received signals.

摘要翻译： 为了减少由接收机通过传播信道接收的信号的干扰，每个信号包括根据频率和时间维度分布并且对应于公共发射信号的符号，接收机通过加权矢量对发射信号和接收信号的估计进行加权， 表示用于在发射器和接收器之间传播信号的通道的时间变化和频率变化的矢量子空间。 这些矢量子空间由矩阵定义，其中一些列被抑制为通道的频率和时间约束的函数。 接收机将加权接收信号的和之差和发射信号的加权估计的函数最小化，以便根据加权向量和接收信号来估计发射信号。

公开(公告)号：US07856052B2

公开(公告)日：2010-12-21

申请号：US11565365

申请日：2006-11-30

申请人： Mark Kent ,  Uri Landau ,  Severine Catreux-Erceg ,  Vinko Erceg ,  Ning Kong ,  Pieter Roux

发明人： Mark Kent ,  Uri Landau ,  Severine Catreux-Erceg ,  Vinko Erceg ,  Ning Kong ,  Pieter Roux

IPC分类号： H03K5/159 ,  H03H7/30 ,  H03H7/40

CPC分类号： H04B7/0413 ,  H04L25/03038 ,  H04L2025/03426 ,  H04L2025/03471 ,  H04L2025/03617 ,  H04L2025/03662 ,  H04L2025/037

摘要： Methods and systems for processing signals in a receiver are disclosed herein and may include updating a plurality of filter taps utilizing at least one channel response vector and at least one correlation vector, for a plurality of received clusters, based on initialized values related to the at least one channel response vector and the at least one correlation vector. At least a portion of the received signal clusters may be filtered utilizing at least a portion of the updated plurality of filter taps. The update may be repeated whenever a specified signal-to-noise ratio (SNR) for the received signal clusters is reached. The initialized values may be updated during a plurality of iterations, and the update may be repeated whenever a specified number of the plurality of iterations is reached.

摘要翻译： 本文公开了一种用于在接收机中处理信号的方法和系统，并且可以包括利用至少一个信道响应向量和至少一个相关向量来更新多个滤波器抽头，对于多个接收到的簇，基于与该at 至少一个信道响应向量和所述至少一个相关向量。 可以利用更新的多个滤波器抽头的至少一部分来对接收信号簇的至少一部分进行滤波。 只要达到接收信号簇的指定信噪比（SNR），就可以重新进行更新。 可以在多次迭代期间更新初始化值，并且可以在达到多次迭代的指定次数时重新进行更新。

公开(公告)号：US07844019B2

公开(公告)日：2010-11-30

申请号：US11538341

申请日：2006-10-03

申请人： Oscar E. Agazzi

发明人： Oscar E. Agazzi

IPC分类号： H04L7/00

CPC分类号： H04L7/0062 ,  G01R31/3004 ,  G01R31/3008 ,  G01R31/3016 ,  G01R31/31715 ,  G01R31/318502 ,  G01R31/318552 ,  G01R31/318594 ,  H04B3/23 ,  H04B3/32 ,  H04L1/0054 ,  H04L1/242 ,  H04L7/0334 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03146 ,  H04L25/03267 ,  H04L25/067 ,  H04L25/14 ,  H04L25/4917 ,  H04L25/497 ,  H04L2025/03363 ,  H04L2025/03369 ,  H04L2025/03477 ,  H04L2025/0349 ,  H04L2025/03496 ,  H04L2025/03503 ,  H04L2025/03617 ,  H04L2025/03745

摘要： A method and a timing recovery system for generating a set of clock signals in a system which includes a set of subsystems. Each of the subsystems includes an analog section. The set of clock signals includes a set of sampling clock signals. Each of the analog sections operates in accordance with a corresponding one of the sampling clock signals. For each of the sampling clock signals, a phase error is generated from a corresponding phase detector. The phase errors are filtered by a set of corresponding loop filters. The filtered phase errors are provided to a set of corresponding oscillators to generate phase control signals. The phase control signals are provided to a set of corresponding phase selectors to generate the sampling clock signals.

摘要翻译： 一种用于在包括一组子系统的系统中生成一组时钟信号的方法和定时恢复系统。 每个子系统包括一个模拟部分。 该组时钟信号包括一组采样时钟信号。 每个模拟部分根据相应的一个采样时钟信号进行工作。 对于每个采样时钟信号，从相应的相位检测器产生相位误差。 相位误差由一组相应的环路滤波器滤波。 将滤波的相位误差提供给一组相应的振荡器以产生相位控制信号。 相位控制信号被提供给一组对应的相位选择器以产生采样时钟信号。

公开(公告)号：US20100260252A1

公开(公告)日：2010-10-14

申请号：US12814674

申请日：2010-06-14

申请人： Uri Landau ,  Mark Kent ,  Severine Catreux-Erceg ,  Vinko Erceg

发明人： Uri Landau ,  Mark Kent ,  Severine Catreux-Erceg ,  Vinko Erceg

IPC分类号： H04L27/01

CPC分类号： H04B7/0619 ,  H04B1/7105 ,  H04B1/7115 ,  H04B7/0697 ,  H04L25/03006 ,  H04L2025/03426 ,  H04L2025/03477 ,  H04L2025/03617

摘要： A system and method for processing signals are disclosed. The method may include performing by one or more processors and/or circuits in a wireless device that includes a plurality of transmit and/or receive antennas for one or more of HSDPA, space-time transmit diversity (STTD), Closed Loop, Normal Mode and spatial multiplexing, the one or more processors and/or circuits comprising a minimum mean square error (MMSE) equalizer, generating a plurality of chip-rate synchronously sampled signals utilizing a plurality of received clusters. At least a portion of said generated plurality of chip-rate synchronously sampled signals may be simultaneously equalized in time domain and in spatial domain, based on a plurality of weight values calculated for the plurality of received clusters. The plurality of weight values may be iteratively computed utilizing a time-based adaptation method.

摘要翻译： 公开了一种用于处理信号的系统和方法。 该方法可以包括由无线设备中的一个或多个处理器和/或电路执行，所述无线设备包括用于HSDPA，时空发射分集（STTD），闭环，正常模式中的一个或多个的多个发射和/或接收天线 以及空间复用，所述一个或多个处理器和/或电路包括最小均方误差（MMSE）均衡器，利用多个接收的簇产生多个码片速率的同步采样信号。 基于为多个接收到的簇计算的多个权重值，所述生成的多个码片速率同步采样信号的至少一部分可以在时域和空间域中同时均衡。 可以使用基于时间的适应方法迭代地计算多个权重值。

公开(公告)号：US07801240B2

公开(公告)日：2010-09-21

申请号：US12273436

申请日：2008-11-18

申请人： Oscar E. Agazzi ,  John L. Creigh ,  Mehdi Hatamian ,  David E. Kruse ,  Arthur Abnous ,  Henry Samueli

发明人： Oscar E. Agazzi ,  John L. Creigh ,  Mehdi Hatamian ,  David E. Kruse ,  Arthur Abnous ,  Henry Samueli

IPC分类号： H04B15/00

CPC分类号： H04L7/0062 ,  G01R31/3004 ,  G01R31/3008 ,  G01R31/3016 ,  G01R31/31715 ,  G01R31/318502 ,  G01R31/318552 ,  G01R31/318594 ,  H04B3/23 ,  H04B3/235 ,  H04B3/32 ,  H04L1/0021 ,  H04L1/0047 ,  H04L1/0053 ,  H04L1/0054 ,  H04L1/0059 ,  H04L1/006 ,  H04L1/242 ,  H04L7/0334 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03146 ,  H04L25/03197 ,  H04L25/03203 ,  H04L25/03235 ,  H04L25/03267 ,  H04L25/03987 ,  H04L25/067 ,  H04L25/14 ,  H04L25/4917 ,  H04L25/497 ,  H04L2001/0096 ,  H04L2025/03363 ,  H04L2025/03369 ,  H04L2025/03477 ,  H04L2025/0349 ,  H04L2025/03496 ,  H04L2025/03503 ,  H04L2025/03617 ,  H04L2025/03745

摘要： Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.

摘要翻译： 公开了为多对千兆位以太网收发器提供高速解码，增强的功率降低和时钟域划分的各种系统和方法。 ISI补偿分为两个阶段; 第一级补偿由解调器中的发射机的部分响应脉冲整形滤波器的特性引起的ISI分量，第二级补偿由维特比解码器中的多对传输信道的特性引起的ISI分量。 基于从单位深度判决反馈均衡器接收的尾值和系数值的子集，通过从多个判决反馈均衡器向维特比提供输入信号来减小DFE深度来实现高速解码。 通过自适应地截断NEXT，FEXT和回声消除滤波器中的有源抽头，或通过禁用解码器电路部分，如通道响应特性允许，实现功率降低。 生成接收时钟信号，使得其与模拟采样时钟信号在频率上同步，并且相对于采样时钟信号之一具有特定的相位偏移。 调整该相位偏移，使得由于来自数字部分到模拟部分的开关噪声的耦合而导致的系统性能降低被大大减小。

公开(公告)号：US07764733B1

公开(公告)日：2010-07-27

申请号：US11491326

申请日：2006-07-21

申请人： Kok-Wui Cheong

发明人： Kok-Wui Cheong

IPC分类号： H03H7/30

CPC分类号： H04L25/0307 ,  H04L2025/0342 ,  H04L2025/03617

摘要： Methods and apparatus are provided for receiving an input signal. In an embodiment of the invention a current candidate QAM constellation can be selected. A mean squared error of a signal responsive to the input signal can be computed based on the current candidate QAM constellation. The computed mean squared error can be compared to a threshold error value. The invention advantageously allows for relatively efficient and relatively reliable equalization of signals transmitted with an unknown QAM constellation, and allows for relatively efficient and reliable recovery of the unknown QAM constellation.

摘要翻译： 提供了用于接收输入信号的方法和装置。 在本发明的实施例中，可以选择当前候选QAM星座。 可以基于当前候选QAM星座来计算响应于输入信号的信号的均方误差。 计算的均方误差可以与阈值误差值进行比较。 本发明有利地允许用未知QAM星座传输的信号的相对有效且相对可靠的均衡，并且允许相对有效和可靠地恢复未知QAM星座。

公开(公告)号：US20100080277A1

公开(公告)日：2010-04-01

申请号：US12239791

申请日：2008-09-28

申请人： Lin Yang ,  Syang-Myau Hwang ,  Qian Zhuang ,  Jun Lu ,  Shue-Lee Chang

发明人： Lin Yang ,  Syang-Myau Hwang ,  Qian Zhuang ,  Jun Lu ,  Shue-Lee Chang

IPC分类号： H04L27/01

CPC分类号： H04L25/03057 ,  H04L2025/03617 ,  H04L2025/03662 ,  H04L2025/03668 ,  H04L2025/037

摘要： A method used in a time domain equalizer is provided. A method comprising the steps of: providing a time domain equalizer comprising a feed forward equalizer and a feedback equalizer; and using a conjugate gradient iteration in order to calculate a set of coefficients of the time domain equalizer.

摘要翻译： 提供了一种在时域均衡器中使用的方法。 一种方法，包括以下步骤：提供包括前馈均衡器和反馈均衡器的时域均衡器; 并使用共轭梯度迭代来计算时域均衡器的一组系数。

公开(公告)号：US20100054324A1

公开(公告)日：2010-03-04

申请号：US12201487

申请日：2008-08-29

申请人： John Francis Bulzacchelli ,  Gautam Gangasani ,  Mounir Meghelli ,  Sergey V. Rylov ,  Michael A. Sorna ,  Steven J. Zier

发明人： John Francis Bulzacchelli ,  Gautam Gangasani ,  Mounir Meghelli ,  Sergey V. Rylov ,  Michael A. Sorna ,  Steven J. Zier

IPC分类号： H03H7/40

CPC分类号： H04L25/03057 ,  H04L2025/0349 ,  H04L2025/03617

摘要： A decision feedback equalizer (DFE) and method include summer circuits configured to add a dynamic feedback tap to a received input to provide a sum and to add a speculative static tap to the sum. Sense amplifiers are configured to receive outputs of the summer circuits and evaluate the outputs of the summer circuits in accordance with a clock signal. A passgate multiplexer is configured to receive outputs from sense amplifiers wherein the multiplexer is clock-gated for isolation of subsequent circuitry from the outputs of the sense amplifiers during a precharge period. A gating circuit is configured to perform gating of a select signal output from a second circuit portion with a clock signal and to enable the isolation of the subsequent circuitry by the multiplexer during the precharge period. A regenerative buffer is coupled to the multiplexer to maintain an output of the multiplexer during the precharge period, to provide the select signal for a passgate multiplexer in the second circuit portion of the DFE and to drive the dynamic feedback tap on the first circuit portion of the DFE.

摘要翻译： 决策反馈均衡器（DFE）和方法包括配置为向所接收的输入添加动态反馈抽头以提供和并且为该和添加推测静态抽头的加法电路。 检测放大器被配置为接收加法电路的输出并根据时钟信号来估计加法电路的输出。 门控多路复用器被配置为接收来自读出放大器的输出，其中多路复用器是时钟选通的，用于在预充电期间将后续电路与读出放大器的输出隔离。 选通电路被配置为利用时钟信号来执行从第二电路部分输出的选择信号的门控，并且能够在预充电期间使多路复用器能够隔离后续电路。 再生缓冲器耦合到多路复用器以在预充电周期期间保持多路复用器的输出，以便为DFE的第二电路部分中的通道门多路复用器提供选择信号，并且在DFE的第一电路部分上驱动动态反馈抽头 DFE。