公开(公告)号：US11217571B2

公开(公告)日：2022-01-04

申请号：US16977172

申请日：2019-03-05

申请人： MITSUBISHI ELECTRIC CORPORATION

发明人： Julien Morand ,  Remi Perrin ,  Roberto Mrad ,  Jeffrey Ewanchuk ,  Stefan Mollov

IPC分类号： H01L25/11 ,  H01L25/18 ,  H01L25/00

摘要： A power module (1) is disclosed, comprising: first and second substrates (10), each substrate patterned layer of electrically conductive material (12), a plurality of pre-packed power cells (20), positioned between the substrates, each cell comprising: an electrically insulating core (21) embedding at least one power die (22), and two external layers (23) of electrically conductive material on opposite sides of the electrically insulating core (21), said external layers being respectively connected to each patterned layers of the substrates, wherein each external layer of a pre-packed power cell comprises a contact pad (230) connected to a respective contact (220) of the power die through connections arranged in the electrically insulating core (21), said contact pad having a surface area greater than the surface area of the power die electrical contact to which it is connected.

公开(公告)号：US11191192B2

公开(公告)日：2021-11-30

申请号：US16396814

申请日：2019-04-29

申请人： DENSO CORPORATION

发明人： Kazuya Takeuchi ,  Ryota Tanabe

IPC分类号： H05K7/20 ,  H01L23/473 ,  H01L25/11

摘要： In an electric power conversion apparatus, a semiconductor module-cooler unit includes a semiconductor module and a cooler that has cooling pipes stacked with the semiconductor module in a stacking direction. A flow path forming component includes an electronic component main body and has an in-component flow path formed therein. A case receives both the semiconductor module-cooler unit and the flow path forming component therein. A pressure-applying member is arranged in the case to apply pressure to the semiconductor module-cooler unit from a rear side toward a front side in the stacking direction. Moreover, the flow path forming component is fixed to the case. The pressure-applying member, the semiconductor module-cooler unit and the flow path forming component are arranged in alignment with each other in the stacking direction. An in-cooler flow path formed in the cooler and the in-component flow path are fluidically connected with each other in the stacking direction.

公开(公告)号：US11183458B2

公开(公告)日：2021-11-23

申请号：US16464896

申请日：2016-11-30

申请人： Shenzhen Xiuyuan Electronic Technology Co., Ltd.

发明人： Chuan Hu ,  Junjun Liu ,  Yuejin Guo ,  Edward Rudolph Prack

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L23/552 ,  H01L25/065 ,  H01L25/11 ,  H01L25/07 ,  H01L25/075

摘要： An integrated circuit packaging structure and method are provided, the integrated circuit packaging structure includes: a substrate, the substrate being provided with a circuit layer and fine wiring; a chip, the chip being provided with a fine pin and a chip pin; the substrate is provided with at least two of said chips, a chip pin of at least one of said chips being electrically connected to the circuit layer; an insulation patch, the fine wiring being provided on the insulation patch, while the fine pin of the chip is electrically connected to the fine wiring, at least two of said chips being directly electrically connected by means of the fine wiring.

公开(公告)号：US20210351228A1

公开(公告)日：2021-11-11

申请号：US17277894

申请日：2018-12-07

申请人： OSRAM OLED GmbH

发明人： Meik WECKBECKER ,  Vincent GROLIER ,  Philipp KREUTER ,  Florian BOESL ,  Michael JOBST

IPC分类号： H01L27/15 ,  H01L33/62 ,  H01L33/60 ,  H01L25/11 ,  H01L33/00

摘要： A light-emitting device includes a multiplicity of light-emitting modules arranged on a first substrate. Each light-emitting module of the multiplicity of light-emitting modules includes a multiplicity of light-emitting components arranged on a second substrate. The second substrate is electrically connected to the first substrate, and includes a common primary lens for the multiplicity of light-emitting components.

公开(公告)号：US20210280724A1

公开(公告)日：2021-09-09

申请号：US17327316

申请日：2021-05-21

申请人： SONY GROUP CORPORATION

发明人： MAKOTO MURAI

IPC分类号： H01L31/024 ,  H01L27/14 ,  H01L25/10 ,  H01L25/11 ,  H01L25/18 ,  H01L25/00 ,  H01L31/0224 ,  H04N5/225 ,  H01L31/0203 ,  H01L27/146

摘要： In a semiconductor device, a first package is provided with a first substrate under which a semiconductor chip configured to output a signal and a first wiring electrically connected to the semiconductor chip are arranged. A second package is provided with a second substrate above which a processing circuit configured to process the output signal, a second wiring electrically connected to the processing circuit, and an encapsulant configured to seal the processing circuit are arranged, the semiconductor chip and the encapsulant being arranged to face each other in a non-contact manner. A connection portion electrically connects the first wiring and the second wiring.

公开(公告)号：US11107761B2

公开(公告)日：2021-08-31

申请号：US16253710

申请日：2019-01-22

申请人： DENSO CORPORATION

发明人： Takanori Kawashima

IPC分类号： H01L23/498 ,  H01L23/495 ,  H01L23/00 ,  H01L25/07 ,  H01L25/10 ,  H01L25/11

摘要： A semiconductor device may include a first conductive plate, a plurality of semiconductor chips disposed on the first conductive plate, and a first external connection terminal connected to the first conductive plate. The plurality of semiconductor chips may include first, second, and third semiconductor chips. The second semiconductor chip may be located between the first semiconductor chip and the third semiconductor chip. A portion of the first conductive plate where the first external connection terminal is connected may be closest to the second semiconductor chip among the first, second, and third semiconductor chips. The first conductive plate may be provided with an aperture located between the portion of the first conductive plate where the first external connection terminal is connected and a portion of the first conductive plate where the second semiconductor chip is connected.

公开(公告)号：US11092990B2

公开(公告)日：2021-08-17

申请号：US16109355

申请日：2018-08-22

申请人： Micron Technology, Inc.

发明人： Trismardawi Tanadi

IPC分类号： H03L7/00 ,  G05F1/66 ,  H01L25/11 ,  G06F1/26 ,  H01L25/10 ,  H01L25/065 ,  H03K5/14 ,  H03K17/22 ,  H03K5/00

摘要： An apparatus including semiconductor dies in a stack. The semiconductor dies are configured to power-up in a staggered manner. Methods for powering up an electronic device include detecting a power-up event with the semiconductor dies in the stack, and responsive to the power-up event, powering up a first semiconductor die in the stack at a first time, and powering up a second semiconductor die in the stack at a second time that is different from the first time.

公开(公告)号：US20210242187A1

公开(公告)日：2021-08-05

申请号：US16967655

申请日：2019-01-14

申请人： Siemens Aktiengesellschaft

发明人： Wilhelm Meyrath ,  Franz Pfleger ,  Peter Prankh ,  Jörg Strogies ,  Bernd Müller ,  Klaus Wilke ,  Matthias Heimann

IPC分类号： H01L25/11 ,  H01L23/473 ,  H01L23/495

摘要： Various embodiments of the teachings herein include power electronic circuits comprising: interconnected power modules, each with a power electronic element and a plurality of capacitors in parallel. The power electronic elements are mounted on a first side of substrate plates. The capacitors are mounted in a plurality of planes one above the other on a second side of the substrate plates. The substrate plates, with the power electronic elements forward and alongside each other, are fixed onto an assembly side of a base circuit carrier.

公开(公告)号：US11075293B2

公开(公告)日：2021-07-27

申请号：US16328670

申请日：2016-09-24

申请人： Intel Corporation

发明人： Jeanette M. Roberts ,  Ravi Pillarisetty ,  Nicole K. Thomas ,  Hubert C. George ,  James S. Clarke

IPC分类号： H01L29/66 ,  H01L29/76 ,  H01L29/775 ,  H01L29/423 ,  H01L29/12 ,  H01L29/06 ,  H01L25/00 ,  H01L25/16 ,  B82Y10/00 ,  H01L23/31 ,  H01L25/18 ,  H01L23/00 ,  H01L25/11 ,  H01L21/56 ,  H01L29/165

摘要： Disclosed herein are qubit-detector die assemblies, as well as related computing devices and methods. In some embodiments, a die assembly may include: a first die having a first face and an opposing second face, wherein a plurality of active qubit devices are disposed at the first face of the first die; and a second die, mechanically coupled to the first die, having a first face and an opposing second face, wherein a plurality of quantum state detector devices are disposed at the first face of the second die; wherein the first faces of the first and second dies face each other.

公开(公告)号：US11056463B2

公开(公告)日：2021-07-06

申请号：US15528883

申请日：2015-12-11

申请人： SONY CORPORATION

发明人： Hiroshi Takahashi ,  Tomofumi Arakawa ,  Minoru Ishida

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L23/528 ,  H01L25/10 ,  H01L23/485 ,  H01L25/065 ,  H01L25/18 ,  G11C5/00 ,  G11C29/00 ,  G11C5/02 ,  H01L25/07 ,  G06F12/00 ,  G11C7/16 ,  H01L27/146 ,  H04N5/378 ,  H01L25/11 ,  G11C5/06 ,  G11C7/10 ,  G11C8/10 ,  H01L27/118 ,  H03K19/0175 ,  H04N5/907 ,  H04N5/225 ,  H04N5/77 ,  H01L23/482 ,  H01L25/075 ,  H01L25/04

摘要： The present technology relates to a semiconductor apparatus, a production method, and an electronic apparatus that enable semiconductor apparatuses to be laminated and the laminated semiconductor apparatuses to be identified. A semiconductor apparatus that is laminated and integrated with a plurality of semiconductor apparatuses, includes a first penetrating electrode for connecting with the other semiconductor apparatuses and a second penetrating electrode that connects the first penetrating electrode and an internal device, the second penetrating electrode being arranged at a position that differs for each of the laminated semiconductor apparatuses. The second penetrating electrode indicates a lamination position at a time of lamination. An address of each of the laminated semiconductor apparatuses in a lamination direction is identified by writing using external signals after lamination. The present technology is applicable to a memory chip and an FPGA chip.