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31.发明公开公开(公告)号：US20240119981A1
公开(公告)日：2024-04-11
申请号：US18176096
申请日：2023-02-28
申请人： DELL PRODUCTS L.P.
发明人： Isaac Q. Wang , Lee B. Zaretsky
摘要： A clock buffer device for a memory module includes a first clock input coupled to an input of a first phase-locked loop (PLL), and a second clock input coupled to an input of a second PLL. An output of the first PLL is selectably coupled to clock output buffers, and an output of the second PLL is selectably coupled to a subset of the clock output buffers. The clock buffer device receives a first indication that a first information handling system is configured to provide a first clock signal on the first clock input but to not provide a second clock signal on the second clock input, and, in response to the indication, couples the output of the first PLL to the clock output buffers and to disables the second PLL.
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公开(公告)号：US20240105261A1
公开(公告)日：2024-03-28
申请号：US17766568
申请日：2020-10-16
发明人： Keizo HIRAGA
CPC分类号： G11C14/0081 , G11C5/148
摘要： A non-volatile storage circuit (10) of an embodiment includes a volatile storage unit (11) that stores information, a non-volatile storage unit (20) into which the information in the volatile storage unit is written by a store operation, and from which the information is read out to the volatile storage unit (11) by a restore operation via a restore path different from a store path in the store operation, a driver unit (12, 15) that receives a power supply and performs the store operation, and a switch unit (13, 14, 16, 17) that shuts off the power supply to the driver unit (12, 15) during the restore operation.
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33.发明公开公开(公告)号：US20240096427A1
公开(公告)日：2024-03-21
申请号：US18518651
申请日：2023-11-24
发明人： Chunghyun RYU , Jaewoong CHOI
CPC分类号： G11C16/30 , G11C5/141 , H02J7/0048 , H02J7/0063 , H02J7/007182 , H02J7/345 , H02J2207/50
摘要： A method of providing an auxiliary power by an auxiliary power supply. The method may include converting an external power to a plurality of charging voltages; charging a charging circuit with a first charging voltage of the plurality of charging voltages; monitoring a voltage of the charging circuit; when capacitance of the charging circuit is less than a first reference capacitance, charging the charging circuit with a second charging voltage of the plurality of charging voltages, the second charging voltage being higher than the first charging voltage by a first voltage amount; and providing an auxiliary power to outside the auxiliary power supply. The auxiliary power may be generated based on the voltage of the charging circuit.
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公开(公告)号：US20240096425A1
公开(公告)日：2024-03-21
申请号：US18218436
申请日：2023-07-05
发明人： Baekkyu Choi , Fuad Badrieh , Thomas H. Kinsley
摘要： Methods, systems, and devices for power regulation for memory systems are described. In one example, a memory system, such as a memory module, may include a substrate, and an input/output component coupled with the substrate and operable to communicate signals with a host system. The memory system may also include one or more memory devices coupled with the substrate and the input/output component and operable to store data for the host system. A memory device of the one or more memory devices may include a power management component in its package with one or more memory dies. The power management component may be coupled with the one or more memory dies, and feedback component, and may be operable to provide one or more supply voltages for the one or more memory dies based on one or more voltages associated with the memory system.
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公开(公告)号：US11934662B2
公开(公告)日：2024-03-19
申请号：US17515596
申请日：2021-11-01
CPC分类号： G06F3/0619 , G06F1/30 , G06F3/0634 , G06F3/0679 , G06F21/88 , G11C5/141 , G11C5/144
摘要： Systems, apparatus and methods are provided for managing a removable solid state storage system for data loss prevention. A method may include maintaining a standby mode for a timer of the removable solid state storage system until the removable solid state storage system is disconnected from an external power supply, setting an operation time interval on the timer, using the timer to count how long the removable solid state storage system has been disconnected, sending an interrupt to a storage controller of the removable solid state storage system from the timer when the timer counts to the operation time Interval, and performing data loss prevention operations using a power supplied by a removable battery.
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公开(公告)号：US11921534B2
公开(公告)日：2024-03-05
申请号：US17400427
申请日：2021-08-12
发明人： Rashid Iqbal
摘要： Various aspects relate to a startup circuit for a bandgap reference circuit, wherein a target voltage value is associated with the bandgap reference circuit, the target voltage value being indicative of a startup condition of the bandgap reference circuit that triggers a stable on-state of the bandgap reference circuit, wherein the startup circuit is configured to: provide a startup voltage at the bandgap reference circuit to trigger a start of an operation of the bandgap reference circuit; receive a feedback voltage, wherein the feedback voltage is representative of a startup condition of the bandgap reference circuit; and either increase the startup voltage at the bandgap reference circuit in the case that a voltage value of the feedback voltage is less than the target voltage value, or stop providing the startup voltage at the bandgap reference circuit in the case that the voltage value of the feedback voltage is equal to or greater than the target voltage value.
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37.发明公开公开(公告)号：US20240062787A1
公开(公告)日：2024-02-22
申请号：US17891858
申请日：2022-08-19
IPC分类号： G11C5/14 , G11C11/412
CPC分类号： G11C5/147 , G11C11/4125
摘要： Described are techniques for generating a supply voltage for an SRAM array using power switching logic. The power switching logic can generate the supply voltage using a first supply rail (supplying a higher voltage) during an active state and using a second supply rail (supplying a lower voltage) during a deep retention state. In some examples, a sensing and recovery (SR) unit is provided to sense a decrease in the second voltage, for instance, during the deep retention state. The SR unit can generate an additional voltage that modifies the supply voltage to be higher than the decreased second voltage, thereby reducing droop and/or noise in the second supply rail. The power switching logic, SR unit, and SRAM array can be co-located or distributed across a computer system. For instance, the power switching logic, SR unit, and SRAM array can be embedded within a System on Chip integrated circuit.
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公开(公告)号：US11907547B2
公开(公告)日：2024-02-20
申请号：US17729207
申请日：2022-04-26
发明人： Liang Yu , Jonathan S. Parry , Xiaojiang Guo
IPC分类号： G06F12/00 , G06F3/06 , G11C16/32 , G06F1/3206 , G11C7/22 , G11C7/10 , G06F1/3215 , G11C16/30 , G11C5/14 , G11C16/04 , H01L25/065 , G06F119/06
CPC分类号： G06F3/0625 , G06F1/3206 , G06F1/3215 , G06F3/0631 , G06F3/0683 , G11C5/14 , G11C7/1045 , G11C7/22 , G11C16/30 , G11C16/32 , G06F2119/06 , G11C16/0483 , H01L25/0657 , H01L2225/06562
摘要： Memory device might include a controller configured to cause the memory device to determine whether the memory device is waiting to initiate a next phase of an access operation, and in response to determining that the memory device is waiting to initiate the next phase, determine whether there is sufficient available current budget to initiate the next phase in a selected operating mode in response to at least the priority token of the memory device, an expected peak current magnitude for the next phase in the selected operating mode, and additional expected peak current magnitudes for other memory devices. In response to determining that there is sufficient available current budget to initiate the next phase in the selected operating mode, the memory device might output the expected peak current magnitude for the next phase in the selected operating mode from the memory device.
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公开(公告)号：US11901034B2
公开(公告)日：2024-02-13
申请号：US17331226
申请日：2021-05-26
发明人： Jason Guo
CPC分类号： G11C5/147 , G05F3/02 , G11C16/0483 , G11C16/08 , G11C16/30 , G11C5/145 , G11C8/08 , G11C2211/5631
摘要： A memory device comprising multiple memory planes is disclosed. The memory device further comprises a first pump set coupled with the multiple memory planes, and configured to supply a first output voltage to multiple linear regulators during a steady phase, and a second pump set coupled with the multiple memory planes, and configured to supply a second output voltage to the multiple linear regulators during a ramping phase. The multiple linear regulators can includes a first linear regulator set configured to regulate the first output voltage or the second output voltage to generate a first voltage bias for a first group of word lines of the plurality of memory planes, and a second linear regulator set configured to regulate the first output voltage or the second output voltage to generate a second voltage bias for a second group of word lines of the plurality of memory planes.
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公开(公告)号：US11894094B1
公开(公告)日：2024-02-06
申请号：US17966107
申请日：2022-10-14
发明人： Wu-Der Yang
摘要： An electronic device and a method of controlling an electronic device are provided. The electronic device includes a first transistor having a first resistor, second resistor, first transistor, and second transistor. The second resistor is connected to the first resistor. The first transistor is connected to the first resistor in parallel and has a first bulk. The second transistor is connected to the second resistor in parallel and has a second bulk. The first bulk of the first transistor receives a first voltage and the first bulk of the second transistor receives a second voltage. The first voltage and the second voltage are different.
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