公开(公告)号：US12149578B2

公开(公告)日：2024-11-19

申请号：US17341056

申请日：2021-06-07

Applicant: Intel Corporation

Inventor： Vasily Aristarkhov

IPC: H04L65/70 ,  H04L65/75 ,  H04N19/124 ,  H04N19/159 ,  H04N19/176 ,  H04N19/177 ,  H04N19/36

Abstract: Described herein are video streaming techniques for applications and workloads executed in the cloud. In one example, the cloud server device encodes display frames using low-delay encoding techniques for transmission to a client device. The cloud server device receives an overlay bitstream from a client device, combines the overlay data with the display frames, and encodes the frames for the viewers using statistics from the display frames encoded for the client device and/or from the overlay data. The cloud server device can then transmit the bitstream to a third device for viewing (e.g., to a viewer device or a streaming server device).

公开(公告)号：US12149207B2

公开(公告)日：2024-11-19

申请号：US17323189

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Ofir Degani ,  Assaf Ben-Bassat ,  Ashoke Ravi ,  Ina Shternberg ,  Naor Shay

IPC: H03F1/02 ,  H03F3/21

Abstract: Techniques are disclosed to allow for a switched capacitor digital power amplifier (PA) that operates using high supply voltage levels beyond twice the maximum voltage rating for any of the transistor terminals such as Vds/Vdg/Vsg.

公开(公告)号：US12148734B2

公开(公告)日：2024-11-19

申请号：US17117350

申请日：2020-12-10

Applicant: Intel Corporation

Inventor： Sarah Atanasov ,  Abhishek A. Sharma ,  Bernhard Sell ,  Chieh-Jen Ku ,  Elliot Tan ,  Hui Jae Yoo ,  Noriyuki Sato ,  Travis W. Lajoie ,  Van H. Le ,  Thoe Michaelos

IPC: H01L25/065 ,  H10B12/00 ,  H10B10/00 ,  H10B20/00 ,  H10B41/20 ,  H10B43/20 ,  H10B63/00

Abstract: Disclosed herein are transistors, memory cells, and arrangements thereof. For example, in some embodiments, an integrated circuit (IC) structure may include a plurality of transistors, wherein the transistors are distributed in a hexagonally packed arrangement. In another example, in some embodiments, an IC structure may include a memory cell including an axially symmetric transistor coupled to an axially symmetric capacitor, wherein the axis of the transistor is aligned with the axis of the capacitor.

公开(公告)号：US12148703B2

公开(公告)日：2024-11-19

申请号：US18135067

申请日：2023-04-14

Applicant: Intel Corporation

Inventor： Robert Sankman ,  Robert May

IPC: H01L23/538 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065

Abstract: Embodiments disclosed herein include electronic packages for PoINT architectures. Particularly, embodiments include electronic packages that include reinforcement substrates to minimize warpage. In an embodiment, an electronic package comprises, a reinforcement substrate, a plurality of through substrate vias through the reinforcement substrate, a dielectric substrate over the reinforcement substrate, a cavity into the dielectric substrate, and a component in the cavity.

公开(公告)号：US12147914B2

公开(公告)日：2024-11-19

申请号：US18466981

申请日：2023-09-14

Applicant: Intel Corporation

Inventor： Ajit Singh ,  Bharat Daga ,  Michael Behar

IPC: G06F13/10 ,  G06F13/28 ,  G06F17/16 ,  G06N3/04 ,  G06N3/08 ,  G06N5/046 ,  G06N20/00 ,  G06T9/00 ,  G06T15/20

Abstract: Embodiments described herein provide a processing apparatus comprising compute circuitry to generate neural network data for a convolutional neural network (CNN) and write the neural network data to a memory buffer. The compute circuitry additionally includes a direct memory access (DMA) controller including a hardware codec having encode circuitry and a decode circuitry. The DMA controller reads the neural network data from the memory buffer, encode the neural network data via the encode circuit, writes encoded neural network data to a memory device coupled with the processing apparatus, writes metadata for the encoded neural network data to the memory device coupled with the processing apparatus, and decodes encoded neural network data via the decode circuit in response to a request from the compute circuitry.

公开(公告)号：US12147302B2

公开(公告)日：2024-11-19

申请号：US17095530

申请日：2020-11-11

Applicant: Intel Corporation

Inventor： Vasanth Ranganathan ,  Joydeep Ray ,  Abhishek R. Appu ,  Nikos Kaburlasos ,  Lidong Xu ,  Subramaniam Maiyuran ,  Altug Koker ,  Naveen Matam ,  James Holland ,  Brent Insko ,  Sanjeev Jahagirdar ,  Scott Janus ,  Durgaprasad Bilagi ,  Xinmin Tian

IPC: G06F11/10 ,  G06F12/0802 ,  G06T1/20 ,  G06T1/60

Abstract: Apparatuses including a graphics processing unit, graphics multiprocessor, or graphics processor having an error detection correction logic for cache memory or shared memory are disclosed. In one embodiment, a graphics multiprocessor includes cache or local memory for storing data and error detection correction circuitry integrated with or coupled to the cache or local memory. The error detection correction circuitry is configured to perform a tag read for data of the cache or local memory to check error detection correction information.

公开(公告)号：US12147288B2

公开(公告)日：2024-11-19

申请号：US17247649

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Nausheen Ansari ,  Ziv Kabiry ,  Gal Yedidia

IPC: G06F1/3296 ,  G06F1/10 ,  G06F3/14

Abstract: In one embodiment, an apparatus includes a port comprising circuitry to couple the apparatus to one or more devices over a DisplayPort (DP)-based link and a processor to generate signals for communication over the DP-based link. The apparatus also includes memory with instructions to cause the processor to initiate a transition to a low power state in devices of the DP-based link by transmitting a sleep pattern signal over the DP-based link, and initiate a transition to an active power state in devices of the DP-based link by transmitting a wake pulse sequence and physical link establishment signal pattern over the DP-based link.

公开(公告)号：US12147286B2

公开(公告)日：2024-11-19

申请号：US17129116

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Anoop Mukker ,  Romesh Trivedi ,  Suresh Nagarajan

IPC: G06F1/32 ,  G06F1/20 ,  G06F1/3221 ,  G06F1/3234

Abstract: Power management circuitry in the solid state drive monitors activity on the plurality of media channels to coordinate an active period and an idle period using credits to manage a power budget for the solid state drive. The power management circuitry to coordinate active and idle periods across components in a workload pipeline in the solid state drive for a given performance target to obtain an optimal power and thermal profile.

公开(公告)号：US12147083B2

公开(公告)日：2024-11-19

申请号：US17123787

申请日：2020-12-16

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Wilfred Gomes ,  Mauro J. Kobrinsky

IPC: G02B6/42 ,  G02B6/12 ,  G02B6/13 ,  H01L25/16

Abstract: Microelectronic assemblies fabricated using hybrid manufacturing for integrating photonic and electronic components, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by bonding at least two IC structures fabricated using different manufacturers, materials, or manufacturing techniques. Before bonding, at least one IC structure may include photonic components such as optical waveguides, electro-optic modulators, and monolithically integrated lenses, and at least one may include electronic components such as electrically conductive interconnects, transistors, and resistors. One or more additional electronic and/or photonic components may be provided in one or more of these IC structures after bonding. For example, an interconnect implemented as an electrically conductive via or a waveguide implemented as a dielectric via may be provided after bonding to extend through one or more of the bonded IC structures.

公开(公告)号：US12146476B2

公开(公告)日：2024-11-19

申请号：US17561605

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Jeff Ku ,  Mark J. Gallina ,  Min Suet Lim ,  Jianfang Zhu

IPC: H05K7/20 ,  F03G7/06

Abstract: Particular embodiments described herein provide for a flexible vapor chamber with shape memory material for an electronic device. In an example, the electronic device can include a flexible vapor chamber and shape memory material coupled to the shape memory material. When the shape memory material is activated, the shape memory material moves a portion of the flexible vapor chamber to a position that helps with heat dissipation of heat collected by the flexible vapor chamber.