公开(公告)号：US20040151023A1

公开(公告)日：2004-08-05

申请号：US10715883

申请日：2003-11-18

Applicant: STMicroelectronics S.r.I. ,  OVONYX Inc.

Inventor： Osama Khouri ,  Ferdinando Bedeschi ,  Claudio Resta

IPC: G11C011/00

CPC classification number: G11C7/04 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/009 ,  G11C2029/5002 ,  G11C2213/79

Abstract: A phase change memory includes a temperature sensor having a resistance variable with temperature with the same law as a phase-change storage element. The temperature sensor is formed by a resistor of chalcogenic material furnishing an electrical quantity that reproduces the relationship between the resistance of a phase change memory cell and temperature; the electrical quantity is processed so as to generate reference quantities as necessary for writing and reading the memory cells. The chalcogenic resistor has the same structure as a memory cell and is programmed with precision, preferably in the reset state.

Abstract translation: 相变存储器包括具有与相变存储元件相同定律的具有温度的电阻变化的温度传感器。 该温度传感器是由一个硫化物材料的电阻器形成的，它提供一个再现相变存储器单元电阻和温度之间的关系的电量; 对电量进行处理，以便产生写入和读取存储单元所需的参考量。 硫属电阻器具有与存储器单元相同的结构，并且精确地编程，优选地处于复位状态。

公开(公告)号：US20040119618A1

公开(公告)日：2004-06-24

申请号：US10632564

申请日：2003-08-01

Applicant: STMicroelectronics Limited ,  STMicroelectronics S.r.I.

Inventor： Philip Mattos ,  Marco Losi

IPC: H03M009/00

CPC classification number: H03H17/0664 ,  G01S19/30

Abstract: A semiconductor integrated circuit for processing a plurality of received broadcast signals, such as GPS signals, is operable in two modes: acquisition and tracking. In an acquisition mode, a separate acquisition engine is used which includes a sample reducer for combining samples of a received signal for correlation with a locally generated version of a GPS code. A serial to parallel converter converts the reduced samples to parallel words which are correlated in parallel with locally generated words of the GPS code.

Abstract translation: 用于处理诸如GPS信号的多个接收的广播信号的半导体集成电路可以以两种模式进行操作：采集和跟踪。 在采集模式中，使用单独的采集引擎，其包括用于组合接收信号的采样以与本地生成的GPS码版本进行相关的采样减速器。 串行到并行转换器将缩减的样本转换成与GPS码的本地生成的字并行相关的并行字。

公开(公告)号：US20040112125A1

公开(公告)日：2004-06-17

申请号：US10696500

申请日：2003-10-29

Applicant: STMicroelectronics S.r.I.

Inventor： Manuela La Rosa ,  Donata Nicolosi ,  Giuseppe Esposito Corcione

IPC: G05D001/00

CPC classification number: F02D41/1401 ,  F02D35/023 ,  F02D41/1405 ,  F02D41/1462 ,  F02D2041/1433 ,  F02D2041/389

Abstract: The invention relates to a virtual sensor of exhaust emissions from a fuel-injection endothermic engine having a combustion chamber in each of its cylinders, a fuel injector serving each combustion chamber, and an electronic fuel-injection control unit. Advantageously, the virtual sensor includes an input interface receiving a signal from at least one pressure sensor for measuring the pressure inside at least one combustion chamber of the engine, a second input interface receiving signals from the electronic fuel-injection control unit, and a calculation block to provide estimates of the amounts of nitrogen compounds and particulates in the emissions based on the pressure and other relevant signals to the engine operation.

Abstract translation: 本发明涉及一种燃料喷射吸热式发动机的虚拟传感器，该燃料喷射吸热发动机在其每个气缸中具有燃烧室，每个燃烧室均配有燃料喷射器，以及电子燃料喷射控制单元。 有利地，虚拟传感器包括输入接口，其接收来自至少一个压力传感器的信号，用于测量发动机的至少一个燃烧室内的压力，接收来自电子燃料喷射控制单元的信号的第二输入接口和计算 根据发动机运行的压力和其他相关信号，提供氮化合物和颗粒物排放量的估算值。

公开(公告)号：US20040103334A1

公开(公告)日：2004-05-27

申请号：US10622835

申请日：2003-07-18

Applicant: STMICROELECTRONICS S.r.I.

Inventor： Francesco Pappalardo ,  Agatino Pennisi

IPC: G06F001/12

CPC classification number: G06F1/06 ,  G06F9/3869

Abstract: A pipeline structure is provided for use in a digital system. The pipeline structure includes stages arranged in a sequence from a first stage for receiving an input of the pipeline structure to a last stage for providing an output of the pipeline structure. At least one intermediate stage is interposed between the first stage and the last stage. The pipeline structure also includes a phase shifting circuit for generating at least one local clock signal for controlling the at least one intermediate stage. The first stage and the last stage are controlled by a main clock signal, the at least one local clock signal is generated from the main clock signal, and the main clock signal and the at least one local clock signal are out of phase. Also provided is a method of operating a pipeline structure that includes stages arranged in a sequence.

Abstract translation: 提供了一种用于数字系统的管道结构。 流水线结构包括以从第一阶段顺序排列的阶段，用于接收流水线结构的输入到用于提供流水线结构的输出的最后阶段。 在第一阶段和最后阶段之间插入至少一个中间阶段。 流水线结构还包括一个移相电路，用于产生至少一个本地时钟信号用于控制至少一个中间级。 第一级和最后级由主时钟信号控制，从主时钟信号产生至少一个本地时钟信号，并且主时钟信号和至少一个本地时钟信号异相。 还提供了一种操作流水线结构的方法，其包括按顺序排列的阶段。

公开(公告)号：US20040083327A1

公开(公告)日：2004-04-29

申请号：US10623474

申请日：2003-07-18

Applicant: STMicroelectronics S.r.I.

Inventor： Paolino Schillaci ,  Salvatore Poli ,  Antonino La Malfa

IPC: G06F012/00

CPC classification number: G11C8/06 ,  G06F12/0653 ,  G11C15/00

Abstract: The invention relates to an automatic decoding method for mapping and selecting a non-volatile memory device having a LPC serial communication interface in the available addressing area on motherboards. A logic structure is incorporated in the memory device, which allows a correct decoding to address the memory to the top of the addressable area or to the bottom of the same area, i.e., in both possible cases. This logic incorporates a non-volatile register whose information is stored in a Content Address Memory to enable the automatic mapping of the memory in the addressable memory area.

Abstract translation: 本发明涉及一种用于映射和选择在主板上的可用寻址区域中具有LPC串行通信接口的非易失性存储器件的自动解码方法。 逻辑结构被结合在存储器件中，其允许正确的解码将存储器寻址到可寻址区域的顶部或相同区域的底部，即在两种可能的情况下。 该逻辑包含非易失性寄存器，其信息存储在内容地址存储器中，以使得可寻址存储器区域中的存储器自动映射。

公开(公告)号：US20040078500A1

公开(公告)日：2004-04-22

申请号：US10634150

申请日：2003-08-04

Applicant: STMicroelectronics S.r.I.

Inventor： Saverio Pezzini

IPC: G06F003/00

CPC classification number: G06F13/385

Abstract: A serial interface for communicating with peripherals may include a circuit for generating pointers to addresses in sections of a memory, and a circuit for serially transferring data from or to at least one peripheral connected to the interface that is coupled to the memory based upon requisite configuration commands. The interface may further include a control register coupled to the memory and to the serial transfer circuit for controlling data to be transmitted or received. The interface does not require that an external controller provide configuration commands each time data is transmitted or received because the memory sections for storing data may be divided in distinct memory spaces. That is, each memory space may store data for a respective peripheral connected to the interface. Moreover, another memory section may be used to store all of the configuration commands of the interface required for communicating with the peripherals.

Abstract translation: 用于与外围设备进行通信的串行接口可以包括用于在存储器的部分中产生指向地址的指针的电路，以及用于根据必要配置，连接到连接到接口的至少一个外围设备的串行数据传输数据的电路 命令。 接口还可以包括耦合到存储器和串行传输电路的控制寄存器，用于控制要发送或接收的数据。 该接口不要求外部控制器在每次发送或接收数据时都提供配置命令，因为用于存储数据的存储器部分可以分成不同的存储空间。 也就是说，每个存储器空间可以存储连接到接口的相应外设的数据。 此外，可以使用另一个存储器部分来存储与外围设备进行通信所需的接口的所有配置命令。

公开(公告)号：US20040059765A1

公开(公告)日：2004-03-25

申请号：US10615446

申请日：2003-07-08

Applicant: STMicroelectronics S.r.I.

Inventor： Gianguido Rizzotto ,  Paolo Amato ,  Domenico Porto

IPC: G06F017/14

CPC classification number: G06N99/002 ,  B82Y10/00

Abstract: A method of performing a Grover's or a Deutsch-Jozsa's quantum algorithm being input with a binary function defined on a space having a basis of vectors of n of qubits includes carrying out a superposition operation over input vectors for generating components of linear superposition vectors referred to a second basis of vectors of nnull1 qubits. An entanglement operation is performed over components of the linear superposition vectors for generating components of numeric entanglement vectors. The method allows a non-negligible time savings because the entanglement operation does not multiply a superposition vector for an entanglement matrix, but generates components of an entanglement vector simply by copying or inverting respective components of the superposition vector depending on values of the binary function. An interference operation is performed over components of the numeric entanglement vectors for generating components of output vectors.

Abstract translation: 使用在具有量子位n的向量的基础的空间上定义的二进制函数来输入Grover或Deutsch-Jozsa的量子算法的方法包括对输入向量执行叠加操作，该输入向量用于生成涉及的线性叠加向量的分量 n + 1量子位向量的第二个基础。 对于用于产生数字纠缠矢量的分量的线性叠加矢量的分量执行纠缠操作。 该方法允许不可忽略的时间节省，因为纠缠操作不会叠加纠缠矩阵的叠加矢量，而是简单地通过根据二进制函数的值复制或反转叠加矢量的各个分量来生成纠缠矢量的分量。 对数字纠缠矢量的分量进行干扰运算，以产生输出矢量的分量。

公开(公告)号：US20040041268A1

公开(公告)日：2004-03-04

申请号：US10456940

申请日：2003-06-06

Applicant: STMicroelectronics S.r.I.

Inventor： Marco Montagnana

IPC: H01L023/48

CPC classification number: H01L23/5223 ,  H01L23/5286 ,  H01L24/06 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A multilayer metal supply rings structure of an integrated circuit comprises at least two parallel perimetral metal rails defined in metal layers of different levels, geometrically superposed one to the other. Each rail is constituted by using definition juxtaposed modules, each module defining on a metal layer parallel segments, longitudinally separated by a separation cut, of each rail, superposed rails of said multilayer structure constituting one supply node being electrically interconnected through a plurality of interconnection vias through dielectric isolation layers between different metal levels. A feature of the multilayer metal supply rings structure is that the segments of each of said perimetral metal rails modularly defined on each metal level belong alternately to one and another supply node upon changing the metal level. A process of defining a multilayer metal supply rings structure is also disclosed.

Abstract translation: 集成电路的多层金属供给环结构包括至少两个平行的周边金属导轨，其以不同级别的金属层限定，几何地彼此重叠。 每个轨道通过使用定义并置的模块构成，每个模块在每个轨道上在金属层上限定由纵向分隔开的纵向隔开的平行段，构成一个供应节点的多层结构的叠置轨道通过多个互连通孔电互连 通过不同金属层之间的介电隔离层。 多层金属供给环结构的特征在于，在每个金属层上模块化地限定的每个所述周边金属轨道的段在改变金属水平时交替地属于一个和另一个供应节点。 还公开了一种限定多层金属供应环结构的方法。

公开(公告)号：US20040029307A1

公开(公告)日：2004-02-12

申请号：US10428338

申请日：2003-05-01

Applicant: STMicroelectronics S.r.I.

Inventor： Francesco Ciovacco ,  Simone Alba ,  Roberto Colombo ,  Chiara Savardi

IPC: H01L021/00

CPC classification number: H01L21/823437 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76804 ,  H01L21/76816

Abstract: A method for manufacturing semiconductor-integrated electronic circuits comprises: depositing an auxiliary layer on a substrate; depositing a layer of screening material on the auxiliary layer; selectively removing the layer of screening material to provide a first opening in the layer of screening material and expose an area of the auxiliary layer; and removing this area of the auxiliary layer to form a second opening in the auxiliary layer, whose cross-section narrows toward the substrate to expose an area of the substrate being smaller than the area exposed by the first opening.

Abstract translation: 一种用于制造半导体集成电子电路的方法包括：在衬底上沉积辅助层; 在辅助层上沉积一层筛选材料; 选择性地去除所述筛选材料层以在所述筛选材料层中提供第一开口并暴露所述辅助层的区域; 并且去除辅助层的该区域以在辅助层中形成第二开口，其横截面朝向衬底变窄，以暴露衬底的区域小于由第一开口暴露的区域。

公开(公告)号：US20030234413A1

公开(公告)日：2003-12-25

申请号：US10414252

申请日：2003-04-14

Applicant: STMicroelectronics S.r.I.

Inventor： Giampiero Sberno ,  Salvatore Torrisi ,  Nicolas Demange

IPC: H01L029/76

CPC classification number: G11C7/18 ,  G11C11/22 ,  G11C2211/4013

Abstract: A ferroelectric semiconductor memory includes an arrangement of memory units comprising at least one row of memory units. The memory units of the at least one row are associated with a respective word line of the arrangement. The arrangement of memory unit includes a plurality of local word lines branching off from the word line associated with the at least one row, each local word line being connected to a respective group of memory units of the line. Selective connection means allow to selectively connect one of the local word lines to the respective word line. The arrangement of memory units further includes a plurality of local plate biasing lines, each one associated with the memory units of a respective group of memory units, for selectively driving the memory units of the respective groups.

Abstract translation: 铁电半导体存储器包括包括至少一行存储器单元的存储器单元的布置。 至少一行的存储器单元与该布置的相应字线相关联。 存储单元的布置包括从与至少一行相关联的字线分支的多个本地字线，每个本地字线连接到线路的相应组的存储器单元。 选择性连接装置允许选择性地将本地字线之一连接到相应的字线。 存储单元的布置还包括多个局部板偏置线，每个板偏置线与相应组的存储单元相关联，用于选择性地驱动各组的存储单元。