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    Method of forming miniaturized polycrystalline silicon gate electrodes using selective oxidation
    403.
    发明授权
    Method of forming miniaturized polycrystalline silicon gate electrodes using selective oxidation 失效
    使用选择性氧化形成小型化多晶硅栅电极的方法

    公开(公告)号：US06979635B1

    公开(公告)日：2005-12-27

    申请号：US10759171

    申请日：2004-01-20

    Applicant: Akif Sultan ,  Qi Xiang ,  Bin Yu

    Inventor： Akif Sultan ,  Qi Xiang ,  Bin Yu

    IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L29/78

    CPC classification number: H01L29/6653 ,  H01L21/28035 ,  H01L21/28123 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/976

    Abstract: Ultra narrow and thin polycrystalline silicon gate electrodes are formed by patterning a polysilicon gate precursor, reducing its width and height by selectively oxidizing its upper and side surfaces, and then removing the oxidized surfaces. Embodiments include patterning the polysilicon gate precursor with an oxide layer thereunder, ion implanting to form deep source/drain regions, forming a nitride layer on the substrate surface on each side of the polysilicon gate precursor, thermally oxidizing the upper and side surfaces of the polysilicon gate precursor thereby consuming silicon, and then removing the oxidized upper and side surfaces leaving a polysilicon gate electrode with a reduced width and a reduced height. Subsequent processing includes forming shallow source/drain extensions, forming dielectric sidewall spacers on the polysilicon gate electrode and then forming metal silicide layers on the upper surface of the polysilicon gate electrode and over the source/drain regions.

    Abstract translation: 通过图案化多晶硅栅极前体，通过选择性地氧化其上表面和侧表面，然后去除氧化表面而减小其宽度和高度来形成超窄和多晶硅栅电极。 实施例包括用其下面的氧化物层图案化多晶硅栅极前体，离子注入以形成深源极/漏极区域，在多晶硅栅极前体的每一侧的衬底表面上形成氮化物层，热氧化多晶硅的上表面和侧表面 从而消耗硅，然后去除氧化的上表面和侧表面，留下具有减小的宽度和降低的高度的多晶硅栅电极。 随后的处理包括形成浅源极/漏极延伸部分，在多晶硅栅电极上形成电介质侧壁间隔物，然后在多晶硅栅极电极的上表面上以及在源极/漏极区域上形成金属硅化物层。

    Damascene tri-gate FinFET
    404.
    发明申请
    Damascene tri-gate FinFET 有权
    大马士革三栅极FinFET

    公开(公告)号：US20050153492A1

    公开(公告)日：2005-07-14

    申请号：US10754559

    申请日：2004-01-12

    Applicant: Shibly Ahmed ,  Haihong Wang ,  Bin Yu

    Inventor： Shibly Ahmed ,  Haihong Wang ,  Bin Yu

    IPC: H01L21/336 ,  H01L29/786 ,  H01L21/338

    CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66795

    Abstract: A method of forming a fin field effect transistor includes forming a fin and forming a source region adjacent a first end of the fin and a drain region adjacent a second end of the fin. The method further includes forming a dummy gate over the fin and forming a dielectric layer around the dummy gate. The method also includes removing the dummy gate to form a trench in the dielectric layer and forming a metal gate in the trench.

    Abstract translation: 形成鳍状场效应晶体管的方法包括形成鳍片并形成与鳍片的第一端相邻的源极区域和与鳍片的第二端部相邻的漏极区域。 该方法还包括在鳍上方形成虚拟栅极，并在虚拟栅极周围形成电介质层。 该方法还包括去除伪栅极以在电介质层中形成沟槽并在沟槽中形成金属栅极。

    System and method for forming stacked fin structure using metal-induced-crystallization
    406.
    发明授权
    System and method for forming stacked fin structure using metal-induced-crystallization 失效
    使用金属诱导结晶形成堆叠鳍结构的系统和方法

    公开(公告)号：US06894337B1

    公开(公告)日：2005-05-17

    申请号：US10768014

    申请日：2004-02-02

    Applicant: Haihong Wang ,  Shibly S. Ahmed ,  Bin Yu

    Inventor： Haihong Wang ,  Shibly S. Ahmed ,  Bin Yu

    IPC: H01L21/20 ,  H01L21/336 ,  H01L27/08 ,  H01L29/786

    CPC classification number: H01L29/785 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/02672 ,  H01L21/2022 ,  H01L29/66795 ,  H01L29/7853

    Abstract: A method facilitates the formation of a stacked fin structure for a semiconductor device that includes a substrate. The method includes forming one or more oxide layers on the substrate and forming one or more amorphous silicon layers interspersed with the one or more oxide layers. The method further includes etching the one or more oxide layers and the one or more amorphous silicon layers to form a stacked fin structure and performing a metal-induced crystallization operation to convert the one or more amorphous silicon layers to one or more crystalline silicon layers.

    Abstract translation: 一种方法有助于形成用于包括衬底的半导体器件的堆叠鳍式结构。 该方法包括在衬底上形成一个或多个氧化物层并形成与该一个或多个氧化物层分开的一个或多个非晶硅层。 该方法还包括蚀刻一个或多个氧化物层和一个或多个非晶硅层以形成堆叠鳍状结构，并执行金属诱导结晶操作以将一个或多个非晶硅层转换成一个或多个结晶硅层。

    Double-gate semiconductor device
    407.
    发明授权
    Double-gate semiconductor device 有权
    双栅半导体器件

    公开(公告)号：US06853020B1

    公开(公告)日：2005-02-08

    申请号：US10290330

    申请日：2002-11-08

    Applicant: Bin Yu ,  Judy Xilin An

    Inventor： Bin Yu ,  Judy Xilin An

    IPC: H01L21/265 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/80

    CPC classification number: H01L29/785 ,  H01L21/26586 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/7856 ,  H01L29/78684 ,  Y10S257/90

    Abstract: A double-gate semiconductor device includes a substrate, an insulating layer, a fin and two gates. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. A first gate is formed on the insulating layer and is located on one side of the fin. A portion of the first gate includes conductive material doped with an n-type dopant. The second gate is formed on the insulating layer and is located on the opposite side of the fin as the first gate. A portion of the second gate includes conductive material doped with a p-type dopant.

    Abstract translation: 双栅半导体器件包括衬底，绝缘层，鳍和两个栅极。 绝缘层形成在基板上，并且鳍形成在绝缘层上。 第一栅极形成在绝缘层上并且位于鳍的一侧。 第一栅极的一部分包括掺杂有n型掺杂剂的导电材料。 第二栅极形成在绝缘层上，并且位于作为第一栅极的鳍片的相对侧上。 第二栅极的一部分包括掺杂有p型掺杂剂的导电材料。

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