公开(公告)号：US07102860B2

公开(公告)日：2006-09-05

申请号：US11059838

申请日：2005-02-17

Applicant: Edward P. Wenzel

Inventor： Edward P. Wenzel

IPC: H02H7/85 ,  H02H9/02

CPC classification number: G06F1/28 ,  G05F1/569 ,  G06F1/26 ,  Y10T307/944

Abstract: A power limiting circuit for power supply that is controlled by a power supply control module includes a shunt regulator having a reference input operatively connected to a voltage input that receives a voltage representative of the power supply control module connected thereto. The shunt regulator is biased on when the voltage at the reference input increases above a reference voltage established at the voltage input. A transistor is operatively connected to the shunt regulator and to an output operatively connected to the power supply control module and has a voltage that is representative of voltage operating the power supply control module. The transistor is biased on from the shunt regulator such that the shunt regulator and transistor form a latch when the voltage at the output reduces below an off voltage level to turn off the power supply, dropping the input voltage, and restarting the power supply in a restart cycle.

公开(公告)号：US20060193077A1

公开(公告)日：2006-08-31

申请号：US11391185

申请日：2006-03-27

Applicant: Michael Callahan

Inventor： Michael Callahan

IPC: G11B21/02 ,  G11B5/596

CPC classification number: G11B5/59605

Abstract: A servo control circuit provides seamless transition between seek and track modes while enabling both rapid seek mode operation and accurate tracking. The control circuit includes an analog-to-digital converter having a non-linear characteristic. The non-linear characteristic provides disproportionately large control voltages to derive speed and settling in the seek mode and essentially linear control voltages in the track mode to provide low noise and accurate tracking operation.

公开(公告)号：US07099098B2

公开(公告)日：2006-08-29

申请号：US10349539

申请日：2003-01-22

Applicant: Baris Posat ,  Kemal Ozanoglu ,  Alessandro Venca

Inventor： Baris Posat ,  Kemal Ozanoglu ,  Alessandro Venca

IPC: G11B5/09

CPC classification number: G11B20/10009 ,  G11B5/02 ,  G11B5/09 ,  G11B2005/0013 ,  G11B2005/0029 ,  H03F1/42 ,  H03F3/45278 ,  H03F2200/36 ,  H03F2200/432 ,  H03F2203/45318 ,  H03F2203/45544 ,  H03F2203/45594 ,  H03F2203/45648

Abstract: An amplifying circuit and method are disclosed for amplifying electrical signals, such as electrical signals generated by the read head of a disk drive. The circuit includes a pair of cross-coupled differential amplifier circuits. Each differential amplifier circuit is asymmetric, including two input transistors of different transistor types. For instance, a first of the two input transistors of each differential amplifier circuit may be a bipolar transistor and a second of the two input transistors may be a field effect transistor. By utilizing asymmetric differential amplifier circuits, a relatively wider operating frequency range is obtained.

公开(公告)号：US20060181225A1

公开(公告)日：2006-08-17

申请号：US11059955

申请日：2005-02-17

Applicant: Thomas Hopkins

Inventor： Thomas Hopkins

IPC: H05B41/36

CPC classification number: H05B41/40

Abstract: A fluorescent lamp assembly includes a fluorescent lamp ballast capable of detecting at least one of a plurality of input signals and generating an output signal. The output signal is associated with a power level that is based on the at least one detected input signal. The fluorescent lamp assembly also includes a fluorescent lamp capable of receiving the output signal and generating light. An intensity of the light is based on the power level associated with the output signal.

公开(公告)号：US07084688B2

公开(公告)日：2006-08-01

申请号：US10929630

申请日：2004-08-30

Applicant: David McClure

Inventor： David McClure

IPC: G06F1/04

CPC classification number: G06F1/10

Abstract: The invention provides a clock delay arrangement accounting for the worst-case delay situation of data signals, which is independent of the layout and technology. It comprises a main clock line; two dummy clock lines, each arranged parallel to the main clock line, and the main clock line disposed between the two dummy clock lines; and a clock source coupled to the main clock line and the two dummy clock lines, adapted to drive said dummy clock lines in phase opposition with respect to the main clock line.

公开(公告)号：US20060165169A1

公开(公告)日：2006-07-27

申请号：US11040658

申请日：2005-01-21

Applicant: Kim Ng ,  Clifford Stein ,  Huisheng Wang

Inventor： Kim Ng ,  Clifford Stein ,  Huisheng Wang

IPC: H04N7/12 ,  H04N11/04 ,  H04N11/02 ,  H04B1/66

CPC classification number: H04N19/87 ,  H04N19/103 ,  H04N19/107 ,  H04N19/114 ,  H04N19/14 ,  H04N19/142 ,  H04N19/17 ,  H04N19/177 ,  H04N19/186 ,  H04N19/20 ,  H04N19/46 ,  H04N19/537 ,  H04N19/593 ,  H04N19/597 ,  H04N19/61

Abstract: A multiple video stream capture and encoding apparatus produces compressed data that represents multiple video streams capturing a common scene. Inages from multiple video streams are analyzed to identify image color segments that are encoded into a composite graph data structure. Corresponding image segments across the multiple video streams are also identified and represented by one node in the composite graph data structure. The composite graph data structure also includes links between pairs of nodes that describe the relationship between the image segments associated with those nodes. The composite graph data structure is updated to represent changes to the image segments in the multiple video streams over time. The composite graph data structure is used to create compressed encoded data for storage and/or transmission.

Abstract translation: 多视频流捕获和编码设备产生代表捕获公共场景的多个视频流的压缩数据。 分析来自多个视频流的入库以识别被编码为复合图形数据结构的图像颜色段。 跨越多个视频流的相应图像段也由复合图形数据结构中的一个节点识别和表示。 复合图数据结构还包括描述与那些节点相关联的图像段之间的关系的节点对之间的链接。 复合图数据结构被更新以表示多个视频流中的图像段随时间的变化。 复合图数据结构用于创建用于存储和/或传输的压缩编码数据。

公开(公告)号：US20060164123A1

公开(公告)日：2006-07-27

申请号：US11393934

申请日：2006-03-30

Applicant: Varghese George

Inventor： Varghese George

IPC: H03K19/0175

CPC classification number: H03K19/01759

Abstract: The present invention is directed to programmable bidirectional buffers and methods for programming such buffers. One method of according to an aspect of the present invention is a method of configuring a bidirectional buffer including first and second signal nodes. The method includes applying a configuration signal on one of the first and second signal nodes and configuring the buffer responsive to the applied configuration signal.

Abstract translation: 本发明涉及用于编程这种缓冲器的可编程双向缓冲器和方法。 根据本发明的一个方面的一种方法是配置包括第一和第二信号节点的双向缓冲器的方法。 该方法包括在第一和第二信号节点之一上应用配置信号并且响应于所应用的配置信号来配置缓冲器。

公开(公告)号：US07079350B1

公开(公告)日：2006-07-18

申请号：US09451746

申请日：1999-11-30

Applicant: Carlo Vertemara ,  Paolo Menegoli ,  Giorgio Pedrazzini

Inventor： Carlo Vertemara ,  Paolo Menegoli ,  Giorgio Pedrazzini

IPC: G11B5/596

CPC classification number: G11B5/54 ,  G11B21/12

Abstract: A control circuit controls a motor assembly having a coil and a movable arm. The control circuit includes a drive circuit that is coupled to the coil and that generates a drive signal in response to a control signal and a speed signal. The control circuit also includes a sensor circuit that is coupled to the drive circuit and to the coil and that generates the speed signal at a level that corresponds to the speed of the arm. In a disk drive, such a circuit can be used to control the movement of a read-write-head assembly during parking and unparking of a read-write head. The circuit monitors the speed of the head and uses this speed information as feedback to maintain the speed of the head within a specified range. This prevents damage to the head and other disk-drive components, particularly in a disk drive that incorporates a head parking platform.

Abstract translation: 控制电路控制具有线圈和可动臂的电动机组件。 控制电路包括耦合到线圈并响应于控制信号和速度信号产生驱动信号的驱动电路。 控制电路还包括耦合到驱动电路和线圈并且以与臂的速度对应的水平产生速度信号的传感器电路。 在磁盘驱动器中，这样的电路可以用于在读写头的停放和取消状态期间控制读写头组件的移动。 该电路监测头部的速度，并使用该速度信息作为反馈，以将头部的速度保持在指定的范围内。 这可以防止头部和其他磁盘驱动器部件的损坏，特别是在包含头部停车平台的磁盘驱动器中。

公开(公告)号：US07072349B2

公开(公告)日：2006-07-04

申请号：US09969137

申请日：2001-10-02

Applicant: Kenton G. DeHart

Inventor： Kenton G. DeHart

IPC: H04L12/56

CPC classification number: G06F5/06 ,  H04L7/0004 ,  H04L7/005 ,  H04L7/02 ,  H04L25/05 ,  H04L47/30 ,  H04L49/3018 ,  H04L49/351

Abstract: A method and ethernet device is disclosed and includes an extended FIFO buffer. The link partner within the ethernet system is in communication with data terminal equipment (DTE). The speed of the link partner determined using a first packet received within the FIFO buffer. Subsequent FIFO buffer reading is optimized based on the determined speed of the link partner, thus for enhancing the inter-packet gap space usage.

公开(公告)号：US07072294B2

公开(公告)日：2006-07-04

申请号：US10785372

申请日：2004-02-24

Applicant: Christian D. Kasper ,  Elmer H. Guritz

Inventor： Christian D. Kasper ,  Elmer H. Guritz

IPC: H04J1/16

CPC classification number: H04L47/30 ,  H04L47/10 ,  H04L47/12 ,  H04L49/90 ,  H04L49/9068 ,  H04L49/9078

Abstract: A method, apparatus and network device for controlling the flow of network data arranged in frames and minimizing congestion is disclosed. A status error indicator is generated within a receive FIFO memory indicative of a frame overflow within the receive FIFO memory. In response to the status error indicator, an early congestion interrupt is generated to a host processor indicative that a frame overflow has occurred within the receive FIFO memory. The incoming frame is discarded and the services of received frames are enhanced by one of either increasing the number of words of a direct memory access (DMA) unit burst size, or modifying the time-slice of other active processes.

Abstract translation: 公开了一种用于控制以帧布置并最小化拥塞的网络数据流的方法，装置和网络设备。 在接收FIFO存储器内产生指示接收FIFO存储器内的帧溢出的状态错误指示符。 响应于状态错误指示器，向主处理器产生指示在接收FIFO存储器内发生帧溢出的早期拥塞中断。 通过增加直接存储器访问（DMA）单元突发大小的字数或修改其他活动进程的时间片之一，丢弃输入帧并接收帧的服务增强。