公开(公告)号：US20220122652A1

公开(公告)日：2022-04-21

申请号：US17564575

申请日：2021-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Kedarnath Balakrishnan ,  Jing Wang ,  Guanhao Shen

IPC: G11C11/406

Abstract: A memory controller interfaces with a random access memory over a memory channel. A refresh control circuit monitors an activate counter which counts a rolling number of activate commands sent over the memory channel to a memory region of the memory. In response to the activate counter being above an intermediate management threshold value, the refresh control circuit only issue a refresh management (RFM) command if there is no REF command currently held at the refresh command circuit for the memory region.

公开(公告)号：US11301410B1

公开(公告)日：2022-04-12

申请号：US17120208

申请日：2020-12-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Gordon Caruk

IPC: G06F13/42 ,  G06F9/54 ,  G06F13/40 ,  G06F15/173 ,  G06F13/364

Abstract: An electronic device includes a requester and a link interface coupled between the requester and a link. The requester is configured to send a request packet to a completer on the link via the link interface. When sending the request packet to the completer, the requester sends, to the completer via the link interface, the request packet with a tag that is not unique with respect to tags in other request packets from the requester that will be in the internal elements of the completer before the request packet is in the internal elements of the completer, but that is unique with respect to tags in other request packets from the requester that will be in the internal elements of the completer while the request packet is in the internal elements of the completer.

公开(公告)号：US11295507B2

公开(公告)日：2022-04-05

申请号：US17091957

申请日：2020-11-06

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Mark Leather ,  Michael Mantor

IPC: G06T15/00 ,  G06F9/48 ,  G06T1/20

Abstract: A graphics processing unit (GPU) or other apparatus includes a plurality of shader engines. The apparatus also includes a first front end (FE) circuit and one or more second FE circuits. The first FE circuit is configured to schedule geometry workloads for the plurality of shader engines in a first mode. The first FE circuit is configured to schedule geometry workloads for a first subset of the plurality of shader engines and the one or more second FE circuits are configured to schedule geometry workloads for a second subset of the plurality of shader engines in a second mode. In some cases, a partition switch is configured to selectively connect the first FE circuit or the one or more second FE circuits to the second subset of the plurality of shader engines depending on whether the apparatus is in the first mode or the second mode.

公开(公告)号：US20220103191A1

公开(公告)日：2022-03-31

申请号：US17125145

申请日：2020-12-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Shrikanth Ganapathy ,  John Kalamatianos

IPC: H03M13/35 ,  G06F11/10 ,  G06F12/0895

Abstract: Systems, apparatuses, and methods for implementing masked fault detection for reliable low voltage cache operation are disclosed. A processor includes a cache that can operate at a relatively low voltage level to conserve power. However, at low voltage levels, the cache is more likely to suffer from bit errors. To mitigate the bit errors occurring in cache lines at low voltage levels, the cache employs a strategy to uncover masked faults during runtime accesses to data by actual software applications. For example, on the first read of a given cache line, the data of the given cache line is inverted and written back to the same data array entry. Also, the error correction bits are regenerated for the inverted data. On a second read of the given cache line, if the fault population of the given cache line changes, then the given cache line's error protection level is updated.

公开(公告)号：US20220100813A1

公开(公告)日：2022-03-31

申请号：US17032314

申请日：2020-09-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sateesh LAGUDU ,  Allen H. RUSH ,  Michael MANTOR ,  Arun Vaidyanathan ANANTHANARAYAN ,  Prasad NAGABHUSHANAMGARI

IPC: G06F17/16 ,  G06F13/28

Abstract: An array processor includes processor element arrays distributed in rows and columns. The processor element arrays perform operations on parameter values. The array processor also includes memory interfaces that are dynamically mapped to mutually exclusive subsets of the rows and columns of the processor element arrays based on dimensions of matrices that provide the parameter values to the processor element arrays. In some cases, the processor element arrays are vector arithmetic logic unit (ALU) processors and the memory interfaces are direct memory access (DMA) engines. The rows of the processor element arrays in the subsets are mutually exclusive to the rows in the other subsets and the columns of the processor element arrays in the subsets are mutually exclusive to the columns in the other subsets. The matrices can be symmetric or asymmetric, e.g., one of the matrices can be a vector having a single column.

公开(公告)号：US20220100686A1

公开(公告)日：2022-03-31

申请号：US17548385

申请日：2021-12-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Vydhyanathan Kalyanasundharam ,  Eric Christopher Morton ,  Bryan P. Broussard ,  Paul James Moyer ,  William Louie Walker

IPC: G06F13/24 ,  G06F13/42

Abstract: Systems, apparatuses, and methods for routing interrupts on a coherency probe network are disclosed. A computing system includes a plurality of processing nodes, a coherency probe network, and one or more control units. The coherency probe network carries coherency probe messages between coherent agents. Interrupts that are detected by a control unit are converted into messages that are compatible with coherency probe messages and then routed to a target destination via the coherency probe network. Interrupts are generated with a first encoding while coherency probe messages have a second encoding. Cache subsystems determine whether a message received via the coherency probe network is an interrupt message or a coherency probe message based on an encoding embedded in the received message. Interrupt messages are routed to interrupt controller(s) while coherency probe messages are processed in accordance with a coherence probe action field embedded in the message.

公开(公告)号：US20220100664A1

公开(公告)日：2022-03-31

申请号：US17132769

申请日：2020-12-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Masab Ahmad ,  Derrick Allen Aguren

IPC: G06F12/0862

Abstract: A system and method for efficiently processing memory requests are described. A processing unit includes at least a processor core, a cache, and a non-cache storage buffer capable of storing data prevented from being stored in the cache. While processing a memory request targeting the non-cache storage buffer, the processor core inspects a flag stored in a tag of the memory request. The processor core prevents data prefetching into one or more of the non-cache storage buffer and the cache based on determining the flag specifies preventing data prefetching into one or more of the non-cache storage buffer and the cache using the target address of the memory request during processing of this instance of the memory request. While processing a prefetch hint instruction, the processor core determines from the tag whether to prevent prefetching.

公开(公告)号：US20220100663A1

公开(公告)日：2022-03-31

申请号：US17116950

申请日：2020-12-09

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Robert B. COHEN ,  Tzu-Wei LIN ,  Anthony J. BYBELL ,  Sudherssen KALAISELVAN ,  James MOSSMAN

IPC: G06F12/0855

Abstract: A processor employs a plurality of op cache pipelines to concurrently provide previously decoded operations to a dispatch stage of an instruction pipeline. In response to receiving a first branch prediction at a processor, the processor selects a first op cache pipeline of the plurality of op cache pipelines of the processor based on the first branch prediction, and provides a first set of operations associated with the first branch prediction to the dispatch queue via the selected first op cache pipeline.

公开(公告)号：US20220100567A1

公开(公告)日：2022-03-31

申请号：US17120215

申请日：2020-12-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Guhan Krishnan

IPC: G06F9/50 ,  G06F13/16 ,  G06T1/60

Abstract: An electronic device includes a memory; a plurality of clients; at least one arbiter circuit; and a management circuit. A given client of the plurality of clients communicates a request to the management circuit requesting an allocation of memory access bandwidth for accesses of the memory by the given client. The management circuit then determines, based on the request, a set of memory access bandwidths including a respective memory access bandwidth for each of the given client and other clients of the plurality of clients that are allocated memory access bandwidth. The management circuit next configures the at least one arbiter circuit to use respective memory access bandwidths from the set of memory access bandwidths for the given client and the other clients for subsequent accesses of the memory.

公开(公告)号：US20220100504A1

公开(公告)日：2022-03-31

申请号：US17032301

申请日：2020-09-25

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Benjamin TSIEN ,  Alexander J. BRANOVER ,  John PETRY ,  Chen-Ping YANG ,  Rostyslav KYRYCHYNSKYI ,  Vydhyanathan KALYANASUNDHARAM

IPC: G06F9/30 ,  G06F9/4401 ,  G06F9/38 ,  G06F9/46 ,  G06F13/40

Abstract: A processing system that includes a shared data fabric resets a first client processor while operating a second client processor. The first client processor is instructed to stop making requests to one or more devices of the shared data fabric. Status communications are blocked between the first client processor and a memory controller, the second client processor, or both, such that the first client processor enters a temporary offline state. The first client processor is indicated as being non-coherent. Accordingly, when the processor is reset some errors and efficiency losses due messages sent during or prior to the reset are prevented.