公开(公告)号：US20240347107A1

公开(公告)日：2024-10-17

申请号：US18616989

申请日：2024-03-26

Applicant: Micron Technology, Inc.

Inventor： Amitava Majumdar ,  Radhakrishna Kotti ,  Rajasekhar Venigalla

IPC: G11C13/00 ,  H01L23/522 ,  H01L23/528 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: G11C13/0028 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0069 ,  H01L23/5226 ,  H01L23/528 ,  H10B63/84 ,  H10N70/231 ,  H10N70/826 ,  G11C2213/52 ,  G11C2213/71 ,  H10N70/841 ,  H10N70/8825

Abstract: Methods, systems, and devices supporting a socket design for a memory device are described. A die may include one or more memory arrays, which each may include any number of word lines and any number of bit lines. The word lines and the bit lines may be oriented in different directions, and memory cells may be located at the intersections of word lines and bit lines. Sockets may couple the word lines and bit lines to associated drivers, and the sockets may be located such that memory cells farther from a corresponding word line socket are nearer a corresponding bit line socket, and vice versa. For example, sockets may be disposed in rows or regions that are parallel to one another, and which may be non-orthogonal to the corresponding word lines and bit lines.

公开(公告)号：US20240346321A1

公开(公告)日：2024-10-17

申请号：US18632708

申请日：2024-04-11

Applicant: Micron Technology, Inc.

Inventor： Febin Sunny ,  Poorna Kale ,  Saideep Tiku

IPC: G06N3/084

CPC classification number: G06N3/084

Abstract: Training an artificial neural network (ANN) can include receiving device design parameters corresponding to a device and operation parameters corresponding to the device. Device throughput characteristics can also be received from a physics solver. Device throughput predictions can be generated utilizing the device design parameters, the operation parameters, and an artificial neural network. A loss gradient can be generated utilizing the device throughput characteristics and the device throughput predictions. The ANN can be trained, utilizing the loss gradient, to generate different device throughput predictions.

公开(公告)号：US20240345982A1

公开(公告)日：2024-10-17

申请号：US18444550

申请日：2024-02-16

Applicant: Micron Technology, Inc.

Inventor： Nikesh AGARWAL ,  Chandana MANJULA LINGANNA

IPC: G06F13/42 ,  G06F13/16

CPC classification number: G06F13/4221 ,  G06F13/1642

Abstract: A memory device comprises a plurality of backend interfaces that are each configured to connect to a respective media device (e.g., DDR, LPDDR DRAM), a plurality of reliability, availability and serviceability (RAS) channel datapaths with each RAS channel datapath connected to one or more backend interfaces, one or more caches that are each connected to at least one RAS channel datapath, and control circuitry. The control circuitry is configured to: in response to receiving a memory access request for a memory location, search a cache of the one or more caches for the requested memory location; and when, in response to the search, the requested memory location is not found in the cache, obtain the requested memory location from a media device connected to the at least one RAS channel datapath. Corresponding methods are also described.

公开(公告)号：US20240345958A1

公开(公告)日：2024-10-17

申请号：US18748668

申请日：2024-06-20

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F12/0864 ,  G06F9/30 ,  G06F9/38 ,  G06F13/16

CPC classification number: G06F12/0864 ,  G06F9/30098 ,  G06F9/3842 ,  G06F13/1684 ,  G06F2212/6042

Abstract: A cache system, having: a first cache set; a second cache set; and a logic circuit coupled to a processor to control the caches based on at least respective first and second registers. When a connection to an address bus receives a memory address from the processor, the logic circuit is configured to: generate a set index from at least the address; and determine whether the generated set index matches with a content stored in the first register or with a content stored in the second register. And, the logic circuit is configured to implement a command via the first cache set in response to the generated set index matching with the content stored in the first register and via the second cache set in response to the generated set index matching with the content stored in the second register.

公开(公告)号：US20240345951A1

公开(公告)日：2024-10-17

申请号：US18630915

申请日：2024-04-09

Applicant: Micron Technology, Inc.

Inventor： Giuseppe Cariello

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7211

Abstract: Methods, systems, and devices for wear leveling techniques using data characteristics are described. The described techniques provide for wear leveling across blocks of a memory system. A controller of the memory system may include additional criteria for determining a destination block for an operation, which may include a characteristic of data associated with the operation. The controller may select a destination block according to both an age of the block and the characteristic of the data. For example, the controller may select a relatively young block for data having a first characteristic and may select a relatively old block for data having a second characteristic. In some cases, the controller may partition free blocks into sub-pools based on an average age of virtual blocks (VBs) associated with each free block.

公开(公告)号：US20240345932A1

公开(公告)日：2024-10-17

申请号：US18630614

申请日：2024-04-09

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm ,  Todd Jackson Plum ,  Mark D. Ingram ,  Scott D. Van De Graaff

IPC: G06F11/30

CPC classification number: G06F11/3034 ,  G06F11/3062 ,  G06F11/3075

Abstract: Methods, systems, and devices for memory device health monitoring logic are described. In accordance with examples as disclosed herein, a memory device may include health monitoring logic configured to monitor a degradation level of the memory device. Further, the health monitoring logic may include a self-check logic to monitor the degradation level of the health monitoring logic. Using the health monitoring logic, the memory device may evaluate and store a health state of the memory device, which may be used to flag a fault in the memory device, among other responsive operations. Additionally, using the self-check logic, the memory device may evaluate and store a health state of the health monitoring logic, which may be used to flag a fault of the previously evaluated health state of the memory device. Based on the self-check flag, a host device may halt or adjust the response operations associated with the memory device.

公开(公告)号：US20240345919A1

公开(公告)日：2024-10-17

申请号：US18755592

申请日：2024-06-26

Applicant: Micron Technology, Inc.

Inventor： Ryan G. Fisher

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1048 ,  G06F11/0757 ,  G06F11/0793

Abstract: Exemplary methods, apparatuses, and systems include performing an initial data integrity scan of a subset of memory at an initial time to determine an initial error rate for the subset of memory. The initial error rate and the initial time are stored. A subsequent integrity scan of the subset of memory is performed at a second time to determine a subsequent error rate for the subset of memory. A difference between the initial error rate and the subsequent error rate is determined. A difference between the initial time and the subsequent time is determined. A remedial action is selected using the difference between the initial error rate and the subsequent error rate and the difference between the initial time and the subsequent time and the remedial action is performed.

公开(公告)号：US20240345755A1

公开(公告)日：2024-10-17

申请号：US18630609

申请日：2024-04-09

Applicant: Micron Technology, Inc.

Inventor： Wenjun Wu ,  Feng Xu

IPC: G06F3/06

CPC classification number: G06F3/0647 ,  G06F3/0625 ,  G06F3/0656 ,  G06F3/0683

Abstract: Methods, systems, and devices for dynamically adjusting data read size are described. A memory system controller may be configured to dynamically adjust a size of data transmitted to a host system based on determining a quantity of data requested by the host system. The memory system controller may support receiving a read command of a first data size, incrementing a counter by the first data size, requesting the data from a memory device according to a second data size, and transmitting the data from the memory device according to a third data size based on the counter. The memory system controller may determine the counter does not satisfy a threshold and configure the third data size as a relatively small quantity of data. However, the memory system controller may determine the counter satisfies the threshold and configure the third data size as a relatively large quantity of data.

公开(公告)号：US20240345754A1

公开(公告)日：2024-10-17

申请号：US18629767

申请日：2024-04-08

Applicant: Micron Technology, Inc.

Inventor： Lei Pan

IPC: G06F3/06

CPC classification number: G06F3/0647 ,  G06F3/0604 ,  G06F3/0679

Abstract: Exemplary methods, apparatuses, and systems include a performance mode manager for controlling performance of a wireless update by selecting a performance mode using rations of allocation. The performance mode manager receives a request to initialize a file transfer from a host using wireless communication. In response to the request, the performance mode manager identifies a size of the file transfer by the memory subsystem. The performance mode manager selects a performance mode from a plurality of performance modes and allocates the available set of memory pages using the performance mode. The performance mode manager receives a file of the file transfer. The performance mode manager programs a first portion of the file at the default bit density to the first portion of memory and a second portion of the file at the reduced bit density to the second portion of memory.

公开(公告)号：US12120100B2

公开(公告)日：2024-10-15

申请号：US17727431

申请日：2022-04-22

Applicant: Micron Technology, Inc.

Inventor： Alberto Troia ,  Antonino Mondello

IPC: H04L9/40 ,  G06F3/06 ,  G06F16/21 ,  G06F16/242 ,  G06F16/2452 ,  G06F16/2453 ,  G06F16/28 ,  H04L9/08 ,  H04L9/32 ,  H04L67/1097

CPC classification number: H04L63/0442 ,  G06F3/0683 ,  G06F16/21 ,  G06F16/242 ,  G06F16/2452 ,  G06F16/24535 ,  G06F16/285 ,  H04L9/0869 ,  H04L9/32 ,  H04L9/3239 ,  H04L9/3247 ,  H04L9/3263 ,  H04L9/3297 ,  H04L63/0876 ,  H04L67/1097

Abstract: The present disclosure includes apparatuses, methods, and systems for secure communication between an intermediary device and a network. An example apparatus includes a memory, and circuitry. The circuitry is configured to determine, in response to receipt of a request for information corresponding to a particular category, an identifier associated with the particular category. The circuitry is further configured to provide, along with a signature, the determined identifier to a network device, wherein the requested information are received in response to the signature being verified by network device.