公开(公告)号：US20100301987A1

公开(公告)日：2010-12-02

申请号：US12787782

申请日：2010-05-26

Applicant: Didier Belot ,  Bernardo Leite ,  Eric Kerherve ,  Jean-Baptiste Begueret

Inventor： Didier Belot ,  Bernardo Leite ,  Eric Kerherve ,  Jean-Baptiste Begueret

IPC: H01F27/28

CPC classification number: H01F19/04 ,  H01F27/2804

Abstract: A millimeter wave transformer including, at its primary, a turn formed of a conductive track made in at least one first metallization level, and, at its secondary, a winding in front of the primary turn, including at least one turn formed of a conductive track made in at least one second metallization level isolated from the at least one first level, the track width of the primary turn being at least equal to the total width of the secondary winding.

Abstract translation: 一种毫米波变压器，包括在其初级时由形成在至少一个第一金属化水平面上的导电轨道形成的转弯，并且在其次级处包括在所述初级匝前面的绕组，所述绕组包括由导电 在至少一个第二金属化水平上形成的至少一个第一金属化水平的轨道，所述主转轮的轨道宽度至少等于所述次级绕组的总宽度。

公开(公告)号：US07843945B2

公开(公告)日：2010-11-30

申请号：US11563473

申请日：2006-11-27

Applicant: Gabriele Luculli

Inventor： Gabriele Luculli

IPC: H04L12/28 ,  H04L12/56

CPC classification number: G06F13/4059

Abstract: An interface having internal conductors to transfer data between a sending circuit and a receiving circuit in an integrated electronic circuit, the receiving circuit including an input buffer capable of receiving data and an output terminal for sending to the sending circuit an item of extraction information on each extraction of a data word from the input buffer, and the sending circuit including an enable circuit capable of activating an enable signal according to an item of availability information representative of the memory space available in the input buffer. The item of availability information is updated in the sending circuit on each transmission of a data word or on each receipt of the item of extraction information.

Abstract translation: 一种具有内部导体的接口，用于在集成电子电路中的发送电路和接收电路之间传送数据，所述接收电路包括能够接收数据的输入缓冲器和输出端子，用于向每个发送电路发送提取信息项 从输入缓冲器提取数据字，并且发送电路包括能够根据表示输入缓冲器中可用的存储器空间的可用性信息项激活使能信号的使能电路。 在每次发送数据字时或每次接收到提取信息项时，在发送电路中更新可用性信息项。

公开(公告)号：US20100295416A1

公开(公告)日：2010-11-25

申请号：US12850126

申请日：2010-08-04

Applicant: Nicolas Abelé ,  Pascal Ancey ,  Alexandre Talbot ,  Karim Segueni ,  Guillaume Bouche ,  Thomas Skotnicki ,  Stéphane Monfray ,  Fabrice Casset

Inventor： Nicolas Abelé ,  Pascal Ancey ,  Alexandre Talbot ,  Karim Segueni ,  Guillaume Bouche ,  Thomas Skotnicki ,  Stéphane Monfray ,  Fabrice Casset

IPC: H02N1/08

CPC classification number: H03H9/2405 ,  H03H3/0072 ,  H03H2009/02496

Abstract: A microresonator comprising a single-crystal silicon resonant element and at least one activation electrode placed close to the resonant element, in which the resonant element is placed in an opening of a semiconductor layer covering a substrate, the activation electrode being formed in the semiconductor layer and being level at the opening.

Abstract translation: 一种微谐振器，包括单晶硅谐振元件和靠近谐振元件放置的至少一个激活电极，其中谐振元件放置在覆盖衬底的半导体层的开口中，激活电极形成在半导体层中 并在开幕式的水平。

公开(公告)号：US07838417B2

公开(公告)日：2010-11-23

申请号：US12512461

申请日：2009-07-30

Applicant: Jerome Lopez

Inventor： Jerome Lopez

IPC: H01L21/4763

CPC classification number: H01L23/3677 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/05554 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48237 ,  H01L2224/49113 ,  H01L2224/4912 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/78 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

Abstract: A semiconductor package includes a support plate made of an electrically non-conducting material. Electrical connection vias are formed outside a chip fixing region provided on the front face of the support plate. Electrical connection wires connect pads on a front of the chip to pads on the front of the support plate associated with the electrical connection vias. The front face of the support plate is further provided with at least one intermediate front layer made of a thermally conducting material extending at least partly below the chip. The rear face of the support plate is provided with at least one rear layer made of a thermally conducting material extending at least partly opposite the front layer. The front and rear layers are connected by vias made of a thermally conducting material that fills through-holes made through the plate.

Abstract translation: 半导体封装包括由不导电材料制成的支撑板。 电连接通孔形成在设置在支撑板的前表面上的芯片固定区域的外部。 电气连接线将芯片前部的焊盘连接到与电气连接通孔相关联的支撑板前部的焊盘。 支撑板的前表面还设置有至少一个由至少部分地在芯片下方延伸的导热材料制成的中间前层。 支撑板的后表面设置有至少一个由至少部分地与前层相对延伸的导热材料制成的后层。 前层和后层通过由导热材料制成的通孔连接，填充通过板制成的通孔。

公开(公告)号：US20100289583A1

公开(公告)日：2010-11-18

申请号：US12781518

申请日：2010-05-17

Applicant: Olivier Touzard ,  Véronique Tournier

Inventor： Olivier Touzard ,  Véronique Tournier

IPC: H03F3/45

CPC classification number: H03G1/0023 ,  H03F3/19 ,  H03F3/45089 ,  H03F2200/294 ,  H03F2203/45392

Abstract: A variable gain amplifier having an input node, a variable current source including a control input coupled to the input node, first and second branches coupled in parallel between a first supply terminal and the variable current source, the first and second branches defining a differential pair arranged to be controlled by first and second differential gain signals and having first and second output terminals, one of the output terminals including an output node of the variable gain amplifier; and a potential divider having a middle node coupled to the first and second output terminals, wherein the middle node is also coupled to the input node by a capacitor.

Abstract translation: 一种具有输入节点的可变增益放大器，包括耦合到输入节点的控制输入的可变电流源，并联耦合在第一电源端子和可变电流源之间的第一和第二支路，第一和第二支路限定差分对 被布置为由第一和第二差分增益信号控制并具有第一和第二输出端，输出端之一包括可变增益放大器的输出节点; 以及具有耦合到所述第一和第二输出端子的中间节点的分压器，其中所述中间节点还通过电容器耦合到所述输入节点。

公开(公告)号：US07827222B2

公开(公告)日：2010-11-02

申请号：US11166564

申请日：2005-06-24

Applicant: Pierre-Yvan Liardet ,  Yannick Teglia

Inventor： Pierre-Yvan Liardet ,  Yannick Teglia

IPC: G06F7/58 ,  G06F7/00

CPC classification number: G06F7/58 ,  G06F7/588 ,  H03K3/84

Abstract: A method and a circuit for detecting a loss in the equiprobable character of a first output bit flow originating from at least one first element of normalization of an initial bit flow, including analyzing the flow rate of the normalization element.

Abstract translation: 一种用于检测源自起始位流的归一化的至少一个第一元素的第一输出位流的等能特性损失的方法和电路，包括分析归一化元件的流量。

公开(公告)号：US07801229B2

公开(公告)日：2010-09-21

申请号：US11710869

申请日：2007-02-26

Applicant: Olivier Isson ,  Fabrice Belveze ,  Fatima Aourik

Inventor： Olivier Isson ,  Fabrice Belveze ,  Fatima Aourik

IPC: H04K1/10 ,  H04L27/28

CPC classification number: H04L25/0232 ,  H04L27/2607 ,  H04L27/2647

Abstract: A method of COFDM demodulation of symbols, each including first carriers conveying data and pilots having their frequency positions varying at least partly from one symbol to the next symbol. The method includes, for each symbol, a step of determining a first estimate of the transfer function of the channel for each carrier in a set of the first carriers of the symbol such that, for the frequency positions of the considered carriers, symbols different from the symbol include pilots, corresponding to a linear combination of second estimates determined for pilots at the frequency of said carrier. The coefficients of the linear combination are determined in iterative fashion, a new coefficient value being equal to the sum of the last value of the coefficient and of a term including the product between an iteration step and an error term, the iteration step being determined in iterative fashion.

Abstract translation: 符号的COFDM解调的方法，每个包括传送数据的第一载波和其频率位置至少部分地从一个符号变化到下一个符号的导频。 该方法包括对于每个符号，确定符号的第一载波的集合中的每个载波的信道的传递函数的第一估计的步骤，使得对于所考虑的载波的频率位置，不同于 符号包括导频，对应于为所述载波的频率处的导频确定的第二估计的线性组合。 以迭代方式确定线性组合的系数，新的系数值等于系数的最后值与包括迭代步骤和误差项之间的乘积的项的和，迭代步骤在 迭代时尚。

公开(公告)号：US07797700B2

公开(公告)日：2010-09-14

申请号：US10831539

申请日：2004-04-23

Applicant: Frederic Robin ,  Alain Artieri ,  Stephane Audrain ,  Jacques Dumarest ,  Vincent Lefftz

Inventor： Frederic Robin ,  Alain Artieri ,  Stephane Audrain ,  Jacques Dumarest ,  Vincent Lefftz

IPC: G06F9/455 ,  G06F9/46 ,  G06K9/36 ,  H04N9/80 ,  H04N5/91 ,  H04N7/173

CPC classification number: G06F9/52 ,  H04N19/42

Abstract: Systems and methods are provided for processing different concurrent tasks by a subsystem managed by a central processor. Each tasks is comprised of successive messages including a first message, intermediate messages, and a last message. Each intermediate message comprises a subtask parameter and a link to the next message that indicates the time when the next message is to be processed. The central processor and the subsystem are connected to a storage memory and several counters associated with respective tasks. The system and method reduce task disruptions of the system.

Abstract translation: 提供了系统和方法，用于通过由中央处理器管理的子系统来处理不同的并发任务。 每个任务由包括第一消息，中间消息和最后消息的连续消息组成。 每个中间消息包括子任务参数和指向下一个消息的链接，指示下一个消息要被处理的时间。 中央处理器和子系统连接到存储存储器和与相应任务相关联的若干计数器。 系统和方法减少系统的任务中断。

公开(公告)号：US07776679B2

公开(公告)日：2010-08-17

申请号：US12175877

申请日：2008-07-18

Applicant: Nicolas Loubet ,  Didier Dutartre ,  Frederic Boeuf

Inventor： Nicolas Loubet ,  Didier Dutartre ,  Frederic Boeuf

IPC: H01L21/8238

CPC classification number: H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639

Abstract: A method for manufacturing silicon wells of various crystallographic orientations in a silicon support, including the steps of: forming a silicon layer having a first orientation on a silicon substrate having a second orientation; forming insulating walls, defining wells extend at least down to the border between the silicon substrate and the silicon layer; performing, in first wells, a chemical vapor etch (CVE) of the silicon layer by means of hydrochloric acid, in an epitaxy reactor, at a temperature ranging between 700° C. and 950° C.; and performing, in the first wells, a vapor-phase epitaxy on the silicon substrate in the presence of a precursor of silicon and hydrochloric acid, at a temperature ranging between 700° C. and 900° C. and up to the upper surface of the silicon layer.

Abstract translation: 一种用于制造硅载体中各种晶体取向硅阱的方法，包括以下步骤：在具有第二取向的硅衬底上形成具有第一取向的硅层; 形成绝缘壁，限定阱至少向下延伸到硅衬底和硅层之间的边界; 在外延反应器中，在700℃至950℃的温度范围内，通过盐酸在第一个阱中进行硅层的化学气相蚀刻（CVE）。 并且在第一个阱中，在硅和盐酸的前体存在下，在700℃和900℃之间的温度下，在硅衬底上进行气相外延，直到 硅层。

公开(公告)号：US07761611B2

公开(公告)日：2010-07-20

申请号：US11328729

申请日：2006-01-10

Applicant: André Roger

Inventor： André Roger

IPC: G06F3/00 ,  G06F13/00

CPC classification number: G06F13/28 ,  G06F13/385

Abstract: The invention relates to a method for organizing the registers of a peripheral in memory, the peripheral including at least one control register to be addressed in memory to store configuration data of the peripheral, one transmission register to be addressed in memory to store data to be transmitted from the memory to the peripheral, and one reception register to be addressed in memory to store data to be transmitted from the peripheral to the memory, the method including: duplicating, within a data memory range, the transmission/reception register to different contiguous addresses; and implementing in memory the control registers at contiguous addresses at the level of a memory range adjacent to the memory range where the transmission/reception register has been duplicated.

Abstract translation: 本发明涉及一种用于组织存储器中外围设备的寄存器的方法，所述外围设备包括要在存储器中寻址的至少一个控制寄存器以存储外围设备的配置数据，要在存储器中寻址的一个发送寄存器以存储数据 从存储器发送到外围设备，以及一个要在存储器中寻址的接收寄存器，用于存储要从外围设备发送到存储器的数据，该方法包括：在数据存储器范围内将发送/接收寄存器复制到不同的连续 地址 并且在与发送/接收寄存器已被复制的存储器范围相邻的存储器范围内的连续地址的存储器中实现控制寄存器。