公开(公告)号：US5521511A

公开(公告)日：1996-05-28

申请号：US233645

申请日：1994-04-26

Applicant: Adriano Lanzi ,  Giovanni Avenia ,  Elia Pagani

Inventor： Adriano Lanzi ,  Giovanni Avenia ,  Elia Pagani

IPC: G01R31/26 ,  G01R31/00 ,  G01R31/02 ,  G01R31/28 ,  G01R31/08

CPC classification number: G01R31/2853

Abstract: A test method whereby a high current is supplied to a first pin of an integrated device to be tested, and the variation in the voltage drop between the first pin and a second pin on the device to be tested is determined; the two pins being connected to two pads in turn connected, inside the device to be tested, by a low-voltage-drop path. The variation in the voltage drop of the device to be tested is compared with the measured nominal variation of an undoubtedly sound device of the same type, to determine any excessive deviation indicative of deficiency. The supply current in fact results in power dissipation, local heating and, consequently, a variation in the resistance of the connecting wires or of the die attachment to the lead frame, the extent of which differs according to whether only one or both of the wires of a two-wire connection to be tested are present, and according to whether the die is attached properly, poorly or badly to the lead frame. This variation in resistance is reflected in the amount or speed by which the detected voltage drop varies, thus enabling sound parts to be distinguished from faulty ones.

Abstract translation: 一种测试方法，其中高电流被提供给要测试的集成器件的第一引脚，并且确定被测器件上的第一引脚和第二引脚之间的电压降的变化; 两个引脚连接到两个焊盘，然后通过低压降路径在待测试的器件内连接。 将要测试的器件的电压降的变化与相同类型的无疑是非常良好的器件的测量名义变化进行比较，以确定指示缺陷的任何过度偏差。 电源电流实际上导致功率耗散，局部加热，并且因此导致连接线或芯片附件到引线框架的电阻的变化，其范围根据是否只有一个或两个电线 存在待测试的两线连接，根据芯片是否正确连接，引线框架不良或不良。 这种电阻变化反映在检测到的电压降变化的量或速度上，从而使得声音部分能够与有缺陷的区别。

公开(公告)号：US5515318A

公开(公告)日：1996-05-07

申请号：US460540

申请日：1995-06-02

Applicant: Paolo Cappeletti ,  Leonardo Ravazzi

Inventor： Paolo Cappeletti ,  Leonardo Ravazzi

IPC: G11C17/00 ,  G11C29/00 ,  G11C29/50 ,  G11C29/56 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C29/50004 ,  G11C29/50 ,  G06F2201/81 ,  G11C16/04 ,  G11C2029/5004 ,  G11C2029/5006

Abstract: A method employing a test structure identical to the memory array whose gate oxide quality is to be determined, except for the fact that the cells are connected electrically parallel to one another. The test structure is so stressed electrically as to extract electrons from the floating gate of the defective-gate-oxide cells and so modify the characteristic of the cell while leaving the charge of the non-defective cells unchanged. In this way, only the threshold of the defective cells is altered. A sub-threshold voltage is then applied to the test structure, and the drain current through the cells, which is related to the presence of at least one defective cell in the structure, is measured. Measurement and analysis of the current-voltage characteristic provides for determining the number of defective cells. The method is suitable for in-line quality control of the gate oxide of EPROM, EEPROM and flash-EEPROM memories.

Abstract translation: 除了电池彼此电并联的事实之外，采用与要确定其栅极氧化物质量的存储器阵列相同的测试结构的方法。 测试结构被电应力地从缺陷栅极氧化物电池的浮动栅极提取电子，并且因此改变电池的特性，同时保持无缺陷电池的电荷不变。 以这种方式，只有有缺陷的单元的阈值被改变。 然后将亚阈值电压施加到测试结构，并且测量与结构中存在至少一个有缺陷单元有关的通过单元的漏极电流。 电流 - 电压特性的测量和分析提供了确定缺陷单元的数量。 该方法适用于EPROM，EEPROM和闪存EEPROM存储器栅极氧化物的在线质量控制。

公开(公告)号：US5508602A

公开(公告)日：1996-04-16

申请号：US128791

申请日：1993-09-28

Applicant: Pierandrea Borgato ,  Claudio Diazzi ,  Albino Pidutti

Inventor： Pierandrea Borgato ,  Claudio Diazzi ,  Albino Pidutti

IPC: H02J1/00 ,  H02M3/155 ,  H02M3/156 ,  H02M7/12 ,  H02M7/217 ,  G05F1/625

CPC classification number: H02M3/156

Abstract: A power supply in which control of the switch-on instant of a power device of a boost-circuit (operating in a discontinuous mode) is implemented by monitoring the current which actually flows through the "fly-back" inductance. The current is monitored on a sensing resistance, and, by the use of a comparator, a signal is produced for enabling/disabling the transfer to an input of a PWM driving circuit of a switch-on signal produced by a null detector. This configuration provide good noise immunity, which is particularly useful in power-factor-correction applications, and reduced power dissipation.

Abstract translation: 通过监视实际上流过“回飞”电感的电流来实现对升压电路的功率器件的接通瞬间（以不连续模式操作）的控制的电源。 在感测电阻上监视电流，并且通过使用比较器，产生用于使能/禁止向由空检测器产生的接通信号的PWM驱动电路的输入的传输的信号。 这种配置提供了良好的抗噪声能力，这在功率因数校正应用中特别有用，并降低了功耗。

公开(公告)号：US5500551A

公开(公告)日：1996-03-19

申请号：US273589

申请日：1994-07-11

Applicant: Santo Puzzolo ,  Raffaele Zambrano ,  Mario Paparo

Inventor： Santo Puzzolo ,  Raffaele Zambrano ,  Mario Paparo

IPC: H01L21/8249 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/06 ,  H01L27/082 ,  H01L29/73 ,  H01L29/732 ,  H01L29/00

CPC classification number: H01L27/0823 ,  H01L21/8222 ,  H01L27/0825

Abstract: A bipolar power transistor and a low voltage bipolar transistor are combined in an emitter switching or a semibridge configuration in an integrated structure. In a version with non-isolated components, the components of the structure are totally or partially superimposed on each other, partly in a first epitaxial layer and partly in a second epitaxial layer, and the low voltage bipolar transistor is situated above the emitter region of the bipolar power transistor which is thus a completely buried active structure. In a version with isolated components, there are two P+ regions in an N- epitaxial layer. The first P+ region constitutes the power transistor base and encloses the N+ emitter region of the power transistor. The second P+ region encloses two N+ regions and one P+ region, constituting the collector, emitter, and base regions respectively of the low voltage transistor. A metallization on the front of the chip provides a connection between the collector contact of the low voltage transistor and the emitter contact of the power transistor.

Abstract translation: 双极功率晶体管和低电压双极晶体管以集成结构组合在发射极开关或半谐振器配置中。 在具有非隔离部件的版本中，结构的部件彼此完全或部分地叠置，部分地在第一外延层中，部分地叠置在第二外延层中，并且低电压双极晶体管位于 双极功率晶体管因此是完全埋入的有源结构。 在具有隔离元件的版本中，在N外延层中有两个P +区。 第一P +区域构成功率晶体管基极并且包围功率晶体管的N +发射极区域。 第二P +区域包围分别构成低压晶体管的集电极，发射极和基极区域的两个N +区域和一个P +区域。 芯片前面的金属化提供了低压晶体管的集电极触点和功率晶体管的发射极触点之间的连接。

公开(公告)号：US5491662A

公开(公告)日：1996-02-13

申请号：US266939

申请日：1994-06-27

Applicant: Saverio Pezzini

Inventor： Saverio Pezzini

IPC: G11C17/00 ,  G06F15/78 ,  G11C16/02 ,  G11C29/00 ,  G11C29/04 ,  G11C29/12 ,  G11C29/48 ,  G11C29/50 ,  G11C16/06

CPC classification number: G11C29/48 ,  G11C29/04 ,  G11C29/50 ,  G11C16/04 ,  G11C2029/5006

Abstract: A method is provided for directly reading the current of cells of a memory forming part of a microcontroller by performing a write operation of the cells and using the existing cell programming logic. For this purpose, the programming voltage supply line is supplied with a low voltage (e.g., 1 V); the word line of the cell for reading is enabled; and a write instruction of a data item having a predetermined logic level (e.g., zero) is performed at the bit corresponding to the cell for reading. By providing an additional pass transistor connected to each reference bit line (RBL) and an additional reference cell enabling line (REF-EN), the reference cells may also be read directly.

Abstract translation: 提供一种通过执行单元的写入操作并使用现有的单元编程逻辑直接读取形成微控制器的一部分的存储器的单元的电流的方法。 为此，编程电压供应线路被提供有低电压（例如1V）; 用于读取的单元格的字线被启用; 并且在与用于读取的单元相对应的位处执行具有预定逻辑电平（例如，零）的数据项的写指令。 通过提供连接到每个参考位线（RBL）和附加参考单元使能线（REF-EN）的附加传输晶体管，也可以直接读取参考单元。

公开(公告)号：US5489876A

公开(公告)日：1996-02-06

申请号：US987151

申请日：1992-12-08

Applicant: Sergio Pernici

Inventor： Sergio Pernici

IPC: H03F3/187 ,  H03F3/26 ,  H03F3/45

CPC classification number: H03F3/265 ,  H03F2200/372

Abstract: The amplifier includes a pair of bipolar input transistors (Q1, Q2), each having a base adapted to receive a differential input signal, a collector and an emitter which is biased by a first fixed current source (M7, M8) of its own and a degeneration resistor (R) which connects the emitters of the two bipolar transistors. The collector of each bipolar transistor is also biased by a second fixed current source (M5, M6) with a smaller current than that of the first source, and the collectors of the two bipolar transistors are furthermore connected to the input terminals of respective MOS amplifier devices (M1, M2, M3, M4, R.sub.L). The amplifier can be made in BCD, BiCMOS or purely CMOS technology, in which case the bipolar transistors are obtained as lateral bipolar transistors.

Abstract translation: 放大器包括一对双极性输入晶体管（Q1，Q2），每一个具有适于接收差分输入信号的基极，由本身的第一固定电流源（M7，M8）偏置的集电极和发射极，以及 连接两个双极晶体管的发射极的退化电阻（R）。 每个双极晶体管的集电极也被具有比第一源极小的电流的第二固定电流源（M5，M6）偏置，并且两个双极晶体管的集电极还连接到各个MOS放大器的输入端 设备（M1，M2，M3，M4，RL）。 放大器可以采用BCD，BiCMOS或纯CMOS技术制造，在这种情况下，双极晶体管可作为横向双极晶体管获得。

公开(公告)号：US5486487A

公开(公告)日：1996-01-23

申请号：US139800

申请日：1993-10-19

Applicant: Giancarlo Ginami ,  Enrico Laurin ,  Silvia Lucherini ,  Bruno Vajana

Inventor： Giancarlo Ginami ,  Enrico Laurin ,  Silvia Lucherini ,  Bruno Vajana

IPC: G11C17/12 ,  H01L27/112 ,  H01L21/266

CPC classification number: H01L27/112 ,  G11C17/12

Abstract: A method of manufacture of a low-capacitance programmed cell structure for read-only memory circuits comprises a field-effect transistor having conventional source and drain regions separated by a channel region overlaid by the gate of the transistor. This ROM memory cell is programmed by a channel implant extending only from the source region for a selected distance into the channel region.

Abstract translation: 制造用于只读存储器电路的低电容编程单元结构的方法包括具有由晶体管的栅极重叠的沟道区隔开的常规源极和漏极区域的场效应晶体管。 该ROM存储器单元通过仅从源极区域延伸一个选定距离进入沟道区域的沟道注入来编程。

公开(公告)号：USRE35121E

公开(公告)日：1995-12-12

申请号：US897443

申请日：1992-06-09

Applicant: Marco Olivo ,  Luigi Pascucci ,  Corrado Villa

Inventor： Marco Olivo ,  Luigi Pascucci ,  Corrado Villa

IPC: H01L27/04 ,  G11C5/14 ,  G11C16/30 ,  H01L21/822 ,  H02M3/07 ,  H02M7/25

CPC classification number: G11C5/145 ,  G11C16/30 ,  H02M3/073

Abstract: The regulation of the output voltage of a voltage multiplier driven by a ring oscillator, an inverter of which is substituted by a NOR gate for providing a terminal through which stopping the oscillation, is effected by controlling the oscillation frequency in function of the current delivered by the voltage multiplier by means of a transistor T1 working as a current generator connected in series with a regulating chain of series-connected diodes by biasing the gate of the transistor with a constant voltage Vref, thus imposing a reference current Iref through the transistor. The voltage signal across the transistor is fed to the input of a first inverter with a preset triggering threshold and the output signal of the inverter is fed through an amplifying and phase-regenerating stage to said terminal for stopping the oscillation of said NOR gate of the ring oscillator. When the discharge current through the regulating chain becomes greater than the imposed current Iref, across the transistor T1 a voltage signal develops which, beyond a certain threshold, determines the switching of the inverter and, through the amplifying and phase-regenerating stage, causes a stop of the oscillation which resumes only when conduction through the regulating chain stops. At steady state the oscillation frequency will result controlled so as to maintain constant the output voltage of the voltage multiplier and to limit the discharge current through the regulating chain thus limiting power consumption.

Abstract translation: 由环形振荡器驱动的电压倍增器的输出电压的调节通过控制振荡频率来实现，所述环形振荡器的逆变器由NOR门用于提供停止振荡的端子， 通过用作电流发生器的晶体管T1的电压倍增器，其通过以恒定电压Vref偏置晶体管的栅极而与串联二极管的调节链串联连接，从而通过晶体管施加参考电流Iref。 晶体管两端的电压信号以预设的触发阈值馈送到第一反相器的输入端，并且反相器的输出信号通过放大和相位再生级馈送到所述端子，以停止所述NOR门的振荡 环形振荡器。 当通过调节链的放电电流变得大于施加的电流Iref时，跨越晶体管T1产生电压信号，超过一定的阈值，确定逆变器的开关，并且通过放大和相位再生阶段， 仅当通过调节链的导通停止时才恢复振荡的停止。 在稳定状态下，振荡频率将受到控制，以保持电压倍增器的输出电压恒定，并限制放电电流通过调节链，从而限制功耗。

公开(公告)号：US5469094A

公开(公告)日：1995-11-21

申请号：US251699

申请日：1994-05-31

Applicant: Maurizio Nessi

Inventor： Maurizio Nessi

IPC: H02P6/08 ,  H03K17/042 ,  H03K17/16 ,  H03B1/00

CPC classification number: H03K17/04213 ,  H03K17/166

Abstract: A fast-discharge switch is controlled by a comparator sensing the voltage difference between the output node and the input node of a driving integrator stage that controls the slew-rate of a power switching output transistor. The fast-discharge switch turns off automatically when the output power transistor reaches (in the case of a MOS transistor) or exits (in the case of a bipolar transistor) saturation. The circuit of the invention accelerates the discharge thus reducing the turn-off delay and is insensitive of load conditions and does not affect the performance of the integrating (driver) stage that control the slew-rate.

Abstract translation: 快速放电开关由比较器控制，该比较器感测输出节点和控制功率开关输出晶体管的转换速率的驱动积分器级的输入节点之间的电压差。 当输出功率晶体管达到（在MOS晶体管的情况下）或退出（在双极晶体管的情况下）饱和时，快速放电开关自动关闭。 本发明的电路加速了放电，从而降低了关断延迟，并且对负载条件不敏感，并且不影响控制转换速率的积分（驱动器）级的性能。

公开(公告)号：US5453678A

公开(公告)日：1995-09-26

申请号：US83721

申请日：1993-06-24

Applicant: Luca Bertolini ,  Roberto Gariboldi

Inventor： Luca Bertolini ,  Roberto Gariboldi

IPC: G05F1/56 ,  G05F1/46 ,  G06K7/00 ,  H02H1/04

CPC classification number: H02H1/043 ,  G05F1/468 ,  G06K7/0008

Abstract: A regulator including a power element between the input terminal and output terminal; and a regulating loop including a differential stage for comparing the output voltage of the regulator with a reference voltage and accordingly driving a gain stage connected to the power element. The output voltage is picked up by the differential stage via a resistive divider, the resistance of which varies according to the value of a logic signal at a control input. When the resistance of the divider changes, the inputs of the differential stage are so unbalanced as to produce an output voltage up or down ramp equal to the slew rate of the regulating loop and proportional to the bias current of the differential stage. Over the up ramp, the shorting protection circuit is turned off for a predetermined time .tau., whereas, over the down ramp, a stage is turned on for absorbing the discharge current of the capacitive load.

Abstract translation: 一种调节器，包括输入端子和输出端子之间的功率元件; 以及调节回路，其包括用于将调节器的输出电压与参考电压进行比较的差分级，并因此驱动连接到功率元件的增益级。 输出电压由差分级通过电阻分压器拾取，电阻分压器根据控制输入端的逻辑信号值而变化。 当分压器的电阻变化时，差分级的输入是不平衡的，以产生输出电压上升或下降斜坡等于调节回路的转换速率并与差动级的偏置电流成正比。 在上升斜坡上，短路保护电路关闭预定时间τ，而在下降斜坡上，一个阶段被接通以吸收容性负载的放电电流。