公开(公告)号：US08323403B2

公开(公告)日：2012-12-04

申请号：US12016225

申请日：2008-01-18

申请人： Dieter Graef ,  Markus Blietz ,  Reinhold Wahlich ,  Alfred Miller ,  Dirk Zemke

发明人： Dieter Graef ,  Markus Blietz ,  Reinhold Wahlich ,  Alfred Miller ,  Dirk Zemke

IPC分类号： C30B29/06

CPC分类号： H01L21/76254 ,  C30B15/00 ,  C30B15/20 ,  C30B29/06 ,  H01L21/3226

摘要： An SOI wafer is constructed from a carrier wafer and a monocrystalline silicon layer having a thickness of less than 500 nm, an excess of interstitial silicon atoms prevailing in the entire volume of the silicon layer. The SOI wafers may be prepared by Czochralski silicon single crystal growth, the condition v/G

摘要翻译： SOI晶片由载体晶片和厚度小于500nm的单晶硅层构成，在硅层的整个体积中存在过量的间隙硅原子。 可以通过Czochralski硅单晶生长制备SOI晶片，在整个晶体截面处在结晶前沿满足条件v / G <（v / G）crit = 1.3×10 -3 cm 2 /（K·min） ，结果是在所生成的硅单晶中存在过量的间隙硅原子; 从该硅单晶分离至少一个施主晶片，将施主晶片与载体晶片的接合以及施主晶片的厚度的减小，结果是厚度小于500nm的硅层与 载体晶片残留。

公开(公告)号：US20120263875A1

公开(公告)日：2012-10-18

申请号：US13407832

申请日：2012-02-29

申请人： Georg Brenninger ,  Alois Aigner ,  Christian Hager

发明人： Georg Brenninger ,  Alois Aigner ,  Christian Hager

IPC分类号： C23C16/00

CPC分类号： C23C16/4585 ,  C23C16/4401 ,  H01L21/6719 ,  H01L21/68735

摘要： An apparatus for depositing a material layer originating from process gas on a substrate wafer, contains: a reactor chamber delimited by an upper dome, a lower dome, and a side wall; a susceptor for holding the substrate wafer during the deposition of the material layer; a preheating ring surrounding the susceptor; a liner, on which the preheating ring is supported in a centered position wherein a gap having a uniform width is present between the preheating ring and the susceptor; and a spacer acting between the liner and the preheating ring, the spacer keeping the preheating ring in the centered position and providing a distance Δ between the preheating ring and the liner.

摘要翻译： 一种用于在基板晶片上沉积源自工艺气体的材料层的装置，包括：由上圆顶，下圆顶和侧壁界定的反应室; 用于在所述材料层的沉积期间保持所述基板晶片的基座; 围绕感受器的预热环; 预热环支撑在其中心位置的衬垫，其中在预热环和基座之间存在具有均匀宽度的间隙; 以及作用在衬套和预热环之间的间隔件，间隔件将预热环保持在居中位置并提供距离＆Dgr; 在预热环和衬套之间。

公开(公告)号：US20120255535A1

公开(公告)日：2012-10-11

申请号：US13426723

申请日：2012-03-22

申请人： Makoto Tagami ,  Hironori Kojima

发明人： Makoto Tagami ,  Hironori Kojima

IPC分类号： B28D5/00 ,  B28D1/08

CPC分类号： B28D5/007 ,  Y02P70/179

摘要： A method for cutting a workpiece with a wire saw includes running at least one saw wire in a lateral direction. A first abrasive grain slurry is supplied to the saw wire on two points that are separated by a predetermined distance in a lateral direction. Cutting of the workpiece is started by moving at least one of the workpiece and the saw wire relative to the other and bringing the workpiece into contact with the saw wire from above at a location between the two points on the saw wire where the first abrasive grain slurry is supplied. A second abrasive grain slurry is supplied to a part of an area where the saw wire meshes with the workpiece.

摘要翻译： 用线锯切割工件的方法包括沿横向运行至少一根锯线。 第一磨粒浆料在横向方向上分开预定距离的两个点处供给到锯线。 通过使工件和锯线中的至少一个相对于另一工件移动并使工件与锯线从上方在锯线上的两点之间的位置处移动，从而开始切割工件，其中第一磨粒 供应浆料 将第二磨料浆料供给到锯线与工件啮合的区域的一部分。

公开(公告)号：US08283262B2

公开(公告)日：2012-10-09

申请号：US12499924

申请日：2009-07-09

申请人： Georg Brenninger ,  Alois Aigner

发明人： Georg Brenninger ,  Alois Aigner

IPC分类号： H01L21/00

CPC分类号： C30B25/14 ,  C23C16/24 ,  C23C16/45502 ,  C23C16/481 ,  Y10T428/24612

摘要： A method for depositing a layer on a semiconductor wafer using chemical vapor deposition (CVD). The method includes providing a chamber having an inlet opening and an outlet opening and a channel joining the inlet opening and the outlet opening, wherein the channel is bounded at the bottom by a plane and at the top by a window transmissive to thermal radiation. A semiconductor wafer is disposed so that a surface of the semiconductor lies in the plane, wherein the window has a center region disposed over the semiconductor wafer and an edge region surrounding the center region and not disposed over the semiconductor wafer. A distance between the plane and the window varies across the chamber, the distance being greater at the edge region than at the center region. A tangent applied to a radial profile of the distance at a boundary between the center region and the edge region forms an angle with the plane of not less than 15° and not more than 25°. A deposition gas is conducted through the channel from the gas inlet opening over the semiconductor wafer to the gas outlet opening, wherein a speed at which the deposition gas is conducted varies over the semiconductor wafer according to the varying distance between the plane and the window.

摘要翻译： 一种使用化学气相沉积（CVD）在半导体晶片上沉积层的方法。 该方法包括提供具有入口开口和出口开口以及连接入口开口和出口开口的通道的腔室，其中通道在底部由平面限定，并且在顶部由通过热辐射透射的窗口限定。 半导体晶片被布置为使得半导体的表面位于平面中，其中窗口具有设置在半导体晶片上方的中心区域和围绕中心区域的边缘区域，并且不设置在半导体晶片上。 平面和窗口之间的距离在整个室内变化，边缘区域的距离大于中心区域。 在中心区域和边缘区域之间的边界处施加到距离的径向轮廓的切线与该平面形成不小于15°且不大于25°的角度。 沉积气体通过通道从半导体晶片上的气体入口开口传导到气体出口开口，其中根据平面和窗口之间的变化距离，沉积气体的传导速度在半导体晶片上变化。

公开(公告)号：US20120240915A1

公开(公告)日：2012-09-27

申请号：US13423350

申请日：2012-03-19

申请人： Anton Huber ,  Wolfgang Gmach ,  Robert Kreuzeder ,  Peter Wiesner

发明人： Anton Huber ,  Wolfgang Gmach ,  Robert Kreuzeder ,  Peter Wiesner

IPC分类号： B28D5/00 ,  B28D1/08

CPC分类号： B23D57/0053 ,  B28D5/0064 ,  B28D5/0076 ,  B28D5/045

摘要： A method for slicing wafers from a workpiece includes providing wire guide rolls that each have a grooved coating with a specific thickness, providing a fixed bearing respectively associated with each wire guide roll and providing a sawing wire including wire sections disposed in a parallel fashion. The wire sections are tensioned between the wire guide rolls and are moved relative to the workpiece so as to perform a sawing operation. The wire guide rolls cooled and the fixed bearings are cooled independently of the wire guide rolls.

摘要翻译： 一种用于从工件切片晶片的方法包括提供每个具有特定厚度的带槽涂层的导丝辊，提供分别与每个线导向辊相关联的固定轴承，并提供包括以平行方式设置的线段的锯线。 线段在线导向辊之间张紧并相对于工件移动，以进行锯切操作。 导丝辊被冷却，固定的轴承独立于导线辊被冷却。

公开(公告)号：US08216361B2

公开(公告)日：2012-07-10

申请号：US13226772

申请日：2011-09-07

申请人： Dieter Knerer ,  Andreas Huber ,  Ulrich Lambert ,  Friedrich Passek

发明人： Dieter Knerer ,  Andreas Huber ,  Ulrich Lambert ,  Friedrich Passek

IPC分类号： C30B29/04

CPC分类号： H01L21/268 ,  H01L29/32 ,  Y10T428/24802 ,  Y10T428/31678

摘要： Monocrystalline semiconductor wafers have defect-reduced regions, the defect-reduced regions having a density of GOI-relevant defects within the range of 0/cm2 to 0.1/cm2 and occupy overall an areal proportion of 10% to 100% of the planar area of the semiconductor wafer, wherein the remaining regions of the semiconductor wafer have a significantly higher defect density than the defect-reduced regions. The wafers may be produced by a method for annealing GOI relevant defects in the wafer, by irradiating defined regions of a side of the semiconductor wafer by laser wherein each location is irradiated with a power density of 1 GW/m2 to 10 GW/m2 for at least 25 ms, wherein the laser emits radiation of a wavelength above the absorption edge of the wafer semiconductor material and wherein the temperature of the wafer rises by less than 20 K as a result of irradiation.

摘要翻译： 单晶半导体晶片具有缺陷减少区域，缺陷区域具有在0 / cm 2至0.1 / cm 2范围内的GOI相关缺陷的密度，并且占整个面积比例为平面面积的10％至100％ 半导体晶片，其中半导体晶片的剩余区域具有比缺陷减少区域显着更高的缺陷密度。 可以通过用于通过用激光照射半导体晶片的侧面的限定区域来对晶片中的GOI相关缺陷进行退火的方法来制造晶片，其中以1GW / m 2至10GW / m 2的功率密度照射每个位置， 至少25ms，其中所述激光器发射波长在所述晶片半导体材料的吸收边缘上方的波长的辐射，并且其中所述晶片的温度作为照射的结果升高小于20K。

公开(公告)号：US20120156970A1

公开(公告)日：2012-06-21

申请号：US13313114

申请日：2011-12-07

申请人： Georg Pietsch

发明人： Georg Pietsch

IPC分类号： B24B1/00

CPC分类号： B24B7/17 ,  B24B7/228 ,  B24B37/08 ,  B24B37/28 ,  H01L21/02013 ,  H01L21/02024

摘要： A method for the simultaneous material-removing processing of both sides of at least three semiconductor wafers includes providing a double-side processing apparatus including two rotating ring-shaped working disks and a rolling apparatus. The carriers are arranged in the double-side processing apparatus and the openings are disposed in the carriers so as to satisfy the inequality: R/e·sin(π/N*)−r/e−1≦1.2 where N* denotes a ratio of the round angle and an angle at which adjacent carriers are inserted into the rolling apparatus with the greatest distance with respect to one another, r denotes a radius of each opening for receiving a respective semiconductor wafer, e denotes a radius of a pitch circle around a midpoint of the carrier on which the opening is arranged, and R denotes a radius of the pitch circle on which the carriers move between the working disks by means of the rolling apparatus.

摘要翻译： 至少三个半导体晶片的两侧的同时进行材料去除处理的方法包括提供包括两个旋转环形工作盘和滚动装置的双面处理设备。 载体布置在双面处理装置中，并且开口设置在载体中以满足不等式：R / e·sin（＆pgr; / N *）-r / e-1＆nlE; 1.2其中N *表示 相邻载体相对于彼此以最大距离插入到滚动装置中的角度和角度的比率，r表示用于接收各个半导体晶片的每个开口的半径，e表示间距的半径 围绕其上布置有开口的载体的中点周围，并且R表示载体在工作盘之间借助于滚动装置移动的节圆的半径。

公开(公告)号：US20120149198A1

公开(公告)日：2012-06-14

申请号：US13392151

申请日：2010-08-11

申请人： Juergen Schwandner

发明人： Juergen Schwandner

IPC分类号： H01L21/306

CPC分类号： H01L21/02008 ,  H01L21/02024

摘要： A method for producing a semiconductor wafer includes a number of steps in order including a bilateral material-removing process followed by rounding off an edge of the wafer and grinding front and back sides of the wafer by holding one side and grinding the other. The front and back are then polished with a polishing cloth including bound abrasives and subsequently treated with an etching medium to carry out a material removal of no more than 1μm on each side. The front side is then polished using a polishing cloth including bound abrasives and the back side is simultaneously polished using a polishing cloth free of abrasives while a polish with abrasives is provided. The edge is then polished followed by polishing the back with a polishing cloth including bound abrasives and simultaneously polishing the front with a cloth free of abrasives while a polish including abrasives is provided.

摘要翻译： 制造半导体晶片的方法包括多个步骤，其包括双面材料去除工艺，随后将晶圆的边缘倒圆，并通过夹持一侧并研磨另一侧来研磨晶片的正面和背面。 然后用包括结合的研磨剂的抛光布抛光正面和背面，然后用蚀刻介质进行处理，以进行每侧不超过1μm的材料去除。 然后使用包括结合磨料的抛光布抛光前侧，并且使用不含磨料的抛光布同时抛光背面，同时提供具有磨料的抛光剂。 然后将边缘抛光，然后用抛光布抛光背面，包括结合的磨料，同时用不含磨料的布抛光前面，同时提供包括研磨剂的抛光剂。

公开(公告)号：US08142885B2

公开(公告)日：2012-03-27

申请号：US11947021

申请日：2007-11-29

申请人： Katsuhiko Nakai ,  Sei Fukushima

发明人： Katsuhiko Nakai ,  Sei Fukushima

IPC分类号： B32B7/02

CPC分类号： H01L21/3225 ,  C30B29/06 ,  C30B33/00 ,  Y10T428/24942 ,  Y10T428/24992

摘要： Silicon wafers and a process for their manufacture wherein both slip dislocation and occurrence of warpage are suppressed include heat treatment to provide wafers having plate-shaped BMDs, a density of BMDs whose diagonal lengths are in a range of 10 nm to 120 nm, of BMDs present in the bulk of the wafer at a distance of 50 μm or more is 1×1011/cm3 or more, and the density of BMDs whose diagonal lengths are 750 nm or more in the wafer bulk is 1×107/cm3 or less, and the interstitial oxygen concentration is 5×1017 atoms/cm3 or less. The process involves low and high temperature heat treating at under defined temperature ramping rates.

摘要翻译： 硅晶片及其制造方法，其中滑动位错和翘曲发生都被抑制包括热处理以提供具有板状BMD的晶片，对角线长度在10nm至120nm范围内的BMD的密度，BMD 以50μm以上的距离存在于晶片本体的1×10 11 / cm 3以上，晶片本体的对角线长度为750nm以上的BMD的密度为1×10 7 / cm 3以下， 间隙氧浓度为5×10 17原子/ cm 3以下。 该过程涉及在限定的温度升高速率下的低温和高温热处理。

公开(公告)号：US08115195B2

公开(公告)日：2012-02-14

申请号：US12406258

申请日：2009-03-18

申请人： Peter Storck ,  Martin Vorderwestner

发明人： Peter Storck ,  Martin Vorderwestner

IPC分类号： H01L21/02

CPC分类号： H01L21/02532 ,  C30B25/183 ,  C30B29/52 ,  H01L21/0245 ,  H01L21/0251

摘要： A multilayer semiconductor wafer has a substrate wafer having a first side and a second side; a fully or partially relaxed heteroepitaxial layer deposited on the first side of the substrate wafer; and a stress compensating layer deposited on the second side of the substrate wafer. The multilayer semiconductor wafer is produced by a method including depositing on a first side of a substrate a fully or partially relaxed heteroepitaxial layer at a deposition temperature; and at the same temperature or before significantly cooling the wafer from the deposition temperature, providing a stress compensating layer on a second side of the substrate.

摘要翻译： 多层半导体晶片具有具有第一面和第二面的基板晶片; 沉积在衬底晶片的第一侧上的完全或部分松弛的异质外延层; 以及沉积在基板晶片的第二侧上的应力补偿层。 多层半导体晶片通过包括在基板的第一侧上以沉积温度沉积完全或部分松弛的异质外延层的方法制造; 并且在相同的温度下或在从沉积温度显着冷却晶片之前，在衬底的第二侧上提供应力补偿层。