公开(公告)号：US20230148253A1

公开(公告)日：2023-05-11

申请号：US18053610

申请日：2022-11-08

申请人： Ambiq Micro, Inc.

发明人： Daniel Martin Cermak ,  Stephen James Sheafor

IPC分类号： G06F3/06

CPC分类号： G06F3/0625 ,  G06F3/0659 ,  G06F3/0679

摘要： A low power caching architecture is disclosed. The architecture includes multiple data memory regions, each including a cache memory. The data memory regions are coupled to a peripheral device. A host processor is operable to control power to each of the plurality of data memory regions. The host processor is operable to power on any of data memory regions and power down any unused data memory regions of the data memory regions. A cache control logic is operable to receive a data request from the host processor. The cache control logic requests the data from the peripheral. The host processor powers on at least one of the data memory regions, and stores the requested data in the cache memory of the powered on data memory region.

公开(公告)号：US11556167B1

公开(公告)日：2023-01-17

申请号：US17814832

申请日：2022-07-25

申请人： Ambiq Micro, Inc.

发明人： Carlos Morales

IPC分类号： G06F1/32 ,  G06F1/3296

摘要： A system for computing devices includes a central processing unit (CPU that is configured to perform in a plurality of power modes, each power mode being pre-defined to have a different code-execution performance capability than remaining ones of the plurality of power modes. The system further includes a sampling peripheral, an electrical output, and a memory device. The memory device is configured to select and execute a specific module from the plurality of modules based on the context-identifying input triggering the specific module. If triggered, each module is executed to receive the context-identifying input from the sampling peripheral, and to operate the CPU in a dedicated power mode of the plurality of power modes.

公开(公告)号：US11520499B1

公开(公告)日：2022-12-06

申请号：US17747410

申请日：2022-05-18

申请人： Ambiq Micro, Inc.

发明人： Daniel Martin Cermak ,  Scott McLean Hanson ,  Yousof Mortazavi ,  Ramakanth Kondagunturi

IPC分类号： G06F3/06

摘要： A low-power system-on-chip includes an originating controller, a fabric, and a power controller. The originating controller is configured to initiate a memory transaction request including a source address. The fabric includes an arbiter configured to receive the memory transaction request and determine a first memory device associated with the memory transaction request. The power controller is configured to selectively change a first memory bank of the first memory device from a first power mode to a second power mode based at least in part on the source address. The fabric is configured to perform a memory operation by (a) receiving stored data from memory storage locations corresponding to the source address when the memory transaction request includes a read request, and (b) sending data included in the memory transaction request to the memory storage locations when the memory transaction request includes a program or a write request.

公开(公告)号：US11172293B2

公开(公告)日：2021-11-09

申请号：US16508062

申请日：2019-07-10

申请人： Ambiq Micro, Inc.

发明人： Arpit Shah ,  Scott McLean Hanson ,  Stephen Howard Nease

IPC分类号： H04R3/04 ,  G06F3/16 ,  G06F3/01 ,  G06F40/205

摘要： A low power voice processing system that includes a plurality of non-audio sensors, at least one microphone system, and a plurality of audio modules, at least some of which can be configured in selected modes. A context determination module is connected to the plurality of audio modules, and further connected to receive input from the plurality of non-audio sensors and the at least one microphone system. The context determination module acts to determine use context for the voice processing system and at least in part selects mode operation of at least some of the plurality of audio modules.

公开(公告)号：US20200321875A1

公开(公告)日：2020-10-08

申请号：US16375391

申请日：2019-04-04

申请人： Ambiq Micro, Inc.

发明人： Ivan Bogue ,  Yousof Mortazavi

IPC分类号： H02M3/158 ,  H03K17/0814

摘要： A buck converter is disclosed that may operate in a low power mode or a high power mode based on a power requirements of a load. In the high power mode, modifications to increase frequency response include a higher polling frequency for a comparator, a lower impedance divider in a feedback circuit, a higher biasing current for a comparator, and larger switches for providing current to a reactive step-down circuit of the buck converter. In the low power mode these modifications are reversed. The buck converter may make use of an improved strong arm comparator and a circuit for sensing presence of an inductor in the reactive step-down circuit.

公开(公告)号：US20200321866A1

公开(公告)日：2020-10-08

申请号：US16375526

申请日：2019-04-04

申请人： Ambiq Micro, Inc.

发明人： Ivan Bogue ,  Yousof Mortazavi

IPC分类号： H02M3/158 ,  H02M3/157

摘要： A buck converter is disclosed that may operate in a low power mode or a high power mode based on a power requirements of a load. In the high power mode, modifications to increase frequency response include a higher polling frequency for a comparator, a lower impedance divider in a feedback circuit, a higher biasing current for a comparator, and larger switches for providing current to a reactive step-down circuit of the buck converter. In the low power mode these modifications are reversed. The buck converter may make use of an improved strong arm comparator and a circuit for sensing presence of an inductor in the reactive step-down circuit.

公开(公告)号：US20200159279A1

公开(公告)日：2020-05-21

申请号：US16773160

申请日：2020-01-27

申请人： Ambiq Micro, Inc.

发明人： Stephen James Sheafor ,  Scott Hanson ,  Donovan Popps

IPC分类号： G06F1/06 ,  H02M3/158 ,  G06F1/3296 ,  G05F1/575 ,  H03L7/00 ,  H03M1/12 ,  H03K17/687 ,  G05F1/56 ,  G01R19/00 ,  G06F13/10 ,  G06F11/34 ,  G06F11/30 ,  G06F1/12 ,  G06F1/3287 ,  G06F1/3237 ,  H03L7/181 ,  H03L7/06 ,  H03L7/18

摘要： A low power autonomous peripheral operative to receive configuration or command data and to perform the designated operation(s) without interaction of a processor.

公开(公告)号：US20190079575A1

公开(公告)日：2019-03-14

申请号：US16013767

申请日：2018-06-20

申请人： Ambiq Micro, Inc.

发明人： Scott McLean Hanson ,  Daniel Martin Cermak ,  Eric Jonathan Deal ,  Stephen James Sheafor ,  Donovan Scott Popps ,  Mark A. Baur

IPC分类号： G06F1/32

摘要： A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.

公开(公告)号：US20190079574A1

公开(公告)日：2019-03-14

申请号：US16005315

申请日：2018-06-11

申请人： Ambiq Micro, Inc.

发明人： Scott McLean Hanson ,  Daniel Martin Cermak ,  Eric Jonathan Deal ,  Stephen James Sheafor ,  Donovan Scott Popps ,  Mark A. Baur

IPC分类号： G06F1/32

摘要： A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.

公开(公告)号：US20190050019A1

公开(公告)日：2019-02-14

申请号：US15674242

申请日：2017-08-10

申请人： Ambiq Micro, Inc.

发明人： Stephen James Sheafor ,  Donovan Scott Popps

IPC分类号： G06F1/08 ,  G06F13/42 ,  G06F1/12

CPC分类号： G06F1/08 ,  G06F1/12 ,  G06F13/00 ,  G06F13/4291 ,  H03K23/58

摘要： A system includes an array of counter/timer units that execute a number of timing and pattern generation functions that are selectable by a processor to which the array is coupled. Counter/timer units may receive as inputs the outputs of other counter/timer units, such as for use as a trigger or clock input as instructed by the processor. Counter/timer units may be instructed to execute functions and be coupled to one another by a processor. The processor may then enable the counter/timer units such they subsequently produce complex outputs without additional inputs from the processor. The outputs of the counter/timer units may be used as interrupts to the processor or be used to drive a peripheral device.