公开(公告)号：US20120217513A1

公开(公告)日：2012-08-30

申请号：US13349430

申请日：2012-01-12

申请人： Naoki TEGA ,  Yasuhiro Shimamoto ,  Yuki Mori ,  Hirotaka Hamamura ,  Hiroyuki Okino ,  Digh Hisamoto

发明人： Naoki TEGA ,  Yasuhiro Shimamoto ,  Yuki Mori ,  Hirotaka Hamamura ,  Hiroyuki Okino ,  Digh Hisamoto

IPC分类号： H01L21/28 ,  H01L29/12

CPC分类号： H01L29/7802 ,  H01L21/0475 ,  H01L21/0485 ,  H01L29/1608 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/45 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/7813

摘要： A SiC MOSFET has a subject that resistance in the source region is increased when annealing for metal silicidation is performed to a source region before forming the gate insulating film, the metal silicide layer of the source region is oxidized by an oxidizing treatment (including oxynitriding treatment) when the gate insulating film is formed. When a metal silicide layer to be formed on the surface of a SiC epitaxial substrate is formed before forming a gate insulating film interface layer (oxide film), and an anti-oxidation film for the metal silicide is formed on the metal silicide layer, it is possible to suppress oxidation of the metal silicide layer by the oxidizing treatment upon forming the gate insulating film interface layer and the resistance of the source region can be decreased without lowering the channel mobility.

摘要翻译： SiC MOSFET具有在形成栅极绝缘膜之前对源极区域进行金属硅化退火时源极区域的电阻增加的对象，源极区域的金属硅化物层通过氧化处理（包括氮氧化处理）被氧化 ）形成栅极绝缘膜。 当在形成栅极绝缘膜界面层（氧化物膜）之前形成在SiC外延基板的表面上形成的金属硅化物层时，在金属硅化物层上形成用于金属硅化物的抗氧化膜， 可以通过在形成栅极绝缘膜界面层时的氧化处理来抑制金属硅化物层的氧化，并且可以降低源极区域的电阻而不降低沟道迁移率。

公开(公告)号：US20100322013A1

公开(公告)日：2010-12-23

申请号：US12873679

申请日：2010-09-01

申请人： Tetsuya Ishimaru ,  Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura

发明人： Tetsuya Ishimaru ,  Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura

IPC分类号： G11C16/04 ,  H01L29/792

CPC分类号： G11C16/0466 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/792

摘要： In a situation where a memory cell includes an ONO film, which comprises a silicon nitride film for charge storage and oxide films positioned above and below the silicon nitride film; a memory gate above the ONO film; a select gate, which is adjacent to a lateral surface of the memory gate via the ONO film; a gate insulator positioned below the select gate; a source region; and a drain region, an erase operation is performed by injecting holes generated by BTBT into the silicon nitride film while applying a positive potential to the source region, applying a negative potential to the memory gate, applying a positive potential to the select gate, and flowing a current from the drain region to the source region, thus improving the characteristics of a nonvolatile semiconductor memory device.

摘要翻译： 在存储单元包括ONO膜的情况下，其包括用于电荷存储的氮化硅膜和位于氮化硅膜上方和下方的氧化膜; 在ONO电影上方的记忆门; 选择栅极，其经由ONO膜与存储栅的侧表面相邻; 位于选择门下方的栅极绝缘体; 源区; 和漏极区域，通过将BTBT产生的空穴注入氮化硅膜，同时向源极区域施加正电位，向存储栅极施加负电位，向选择栅极施加正电位，进行擦除操作，以及 使电流从漏极区域流向源极区域，从而改善非易失性半导体存储器件的特性。

公开(公告)号：US07847343B2

公开(公告)日：2010-12-07

申请号：US12368538

申请日：2009-02-10

申请人： Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura ,  Tetsuya Ishimaru

发明人： Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura ,  Tetsuya Ishimaru

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  G11C16/0433 ,  H01L21/2815 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

摘要： Provided is a nonvolatile semiconductor memory device having a split gate structure, wherein a memory gate is formed over a convex shaped substrate and side surfaces of it is used as a channel. The nonvolatile semiconductor memory device according to the present invention is excellent in read current driving power even if a memory cell is scaled down.

摘要翻译： 提供了一种具有分割栅极结构的非易失性半导体存储器件，其中存储栅极形成在凸形基板上，并且其侧表面用作沟道。 根据本发明的非易失性半导体存储器件即使存储单元按比例缩小也具有优异的读取电流驱动功率。

公开(公告)号：US07751255B2

公开(公告)日：2010-07-06

申请号：US12233670

申请日：2008-09-19

申请人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

发明人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0425 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459

摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

摘要翻译： 提供一种稳定运行半导体非易失性存储器件的操作方案。 当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。 因此，可以验证擦除状态，而不知道任何时变变化。 此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

公开(公告)号：US20090231921A1

公开(公告)日：2009-09-17

申请号：US12389361

申请日：2009-02-19

申请人： Shinichiro Kimura ,  Yasuhiro Shimamoto ,  Digh Hisamoto

发明人： Shinichiro Kimura ,  Yasuhiro Shimamoto ,  Digh Hisamoto

IPC分类号： G11C16/06 ,  H01L21/336 ,  H01L29/792 ,  G11C5/14

CPC分类号： H01L27/11568 ,  H01L29/42328 ,  H01L29/792

摘要： In a nonvolatile semiconductor storage device having a split-gate memory cell including a control gate electrode and a sidewall memory gate electrode and a single-gate memory cell including a single memory gate electrode on the same silicon substrate, the control gate electrode is formed in a first region via a control gate insulating film, the sidewall memory gate electrode is formed in the first region via a charge trapping film, and at the same time, a single memory gate electrode is formed in a second region via the charge trapping film. At this time, the sidewall memory gate electrode and the single memory gate electrode are formed in the same process, and the control gate electrode and the sidewall memory gate electrode are formed so as to be adjacently disposed to each other in a state of being electrically isolated from each other.

摘要翻译： 在具有包括控制栅电极和侧壁存储栅电极的分闸存储单元的非易失性半导体存储器件和在同一硅衬底上包括单个存储栅电极的单栅极存储单元中，形成控制栅电极 经由控制栅极绝缘膜的第一区域，所述侧壁存储栅电极经由电荷捕获膜形成在所述第一区域中，并且同时经由电荷捕获膜在第二区域中形成单个存储器栅电极。 此时，侧壁存储器栅极电极和单个存储器栅极电极以相同的工艺形成，并且控制栅极电极和侧壁存储栅电极形成为在电气的状态下彼此相邻地设置 彼此隔离

公开(公告)号：US07504689B2

公开(公告)日：2009-03-17

申请号：US11182013

申请日：2005-07-15

申请人： Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura ,  Tetsuya Ishimaru

发明人： Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura ,  Tetsuya Ishimaru

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  G11C16/0433 ,  H01L21/2815 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

摘要： Provided is a nonvolatile semiconductor memory device having a split gate structure, wherein a memory gate is formed over a convex shaped substrate and side surfaces of it is used as a channel. The nonvolatile semiconductor memory device according to the present invention is excellent in read current driving power even if a memory cell is scaled down.

摘要翻译： 提供了一种具有分割栅极结构的非易失性半导体存储器件，其中存储栅极形成在凸形基板上，并且其侧表面用作沟道。 根据本发明的非易失性半导体存储器件即使存储单元按比例缩小，读取电流驱动功率也优异。

公开(公告)号：US07268042B2

公开(公告)日：2007-09-11

申请号：US11005015

申请日：2004-12-07

申请人： Digh Hisamoto ,  Kan Yasui

发明人： Digh Hisamoto ,  Kan Yasui

IPC分类号： H01L21/8247

CPC分类号： H01L27/11526 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11531 ,  H01L29/66825

摘要： A nonvolatile semiconductor memory device of a split gate structure having a gate of low resistance suitable to the arrangement of a memory cell array is provided. When being formed of a side wall spacer, a memory gate is formed of polycrystal silicon and then replaced with nickel silicide. Thus, its resistance can be lowered with no effect on the silicidation to the selection gate or the diffusion layer.

摘要翻译： 提供了具有适合于存储单元阵列的布置的具有低电阻的栅极的分离栅极结构的非易失性半导体存储器件。 当由侧壁间隔物形成时，存储栅由多晶硅形成，然后被硅化镍替代。 因此，其电阻可以降低，而对选择栅极或扩散层的硅化物没有影响。

公开(公告)号：US20070207581A1

公开(公告)日：2007-09-06

申请号：US11797839

申请日：2007-05-08

申请人： Kan Yasui ,  Digh Hisamoto ,  Shinichiro Kimura

发明人： Kan Yasui ,  Digh Hisamoto ,  Shinichiro Kimura

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/4232 ,  H01L29/792

摘要： In a split gate type nonvolatile memory cell in which a MOS transistor for a nonvolatile memory using a charge storing film and a MOS transistor for selecting it are adjacently formed, the charge storing characteristic is improved and the resistance of the gate electrode is reduced. In order to prevent the thickness reduction at the corner portion of the charge storing film and improve the charge storing characteristic, a taper is formed on the sidewall of the select gate electrode. Also, in order to stably perform a silicide process for reducing the resistance of the self-aligned gate electrode, the sidewall of the select gate electrode is recessed. Alternatively, a discontinuity is formed between the upper portion of the self-aligned gate electrode and the upper portion of the select gate electrode.

公开(公告)号：US07259422B1

公开(公告)日：2007-08-21

申请号：US11653832

申请日：2007-01-17

申请人： Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura ,  Daisuke Okada

发明人： Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura ,  Daisuke Okada

IPC分类号： H01L29/788

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/66833

摘要： A memory cell includes a selective gate and a memory gate arranged on one side surface of the selective gate. The memory gate includes one part formed on one side surface of the selective gate and the other part electrically isolated from the selective gate and a p-well through an ONO layer formed below the memory gate. A sidewall-shaped silicon oxide is formed on side surfaces of the selective gate, and a sidewall-shaped silicon dioxide layer and a silicon dioxide layer are formed on side surfaces of the memory gate. The ONO layer formed below the memory gate is terminated below the silicon oxide, and prevents generation of a low breakdown voltage region in the silicon oxide near an end of the memory gate during deposition of the silicon dioxide layer.

摘要翻译： 存储单元包括布置在选择栅极的一个侧表面上的选择栅极和存储栅极。 存储器栅极包括形成在选择栅极的一个侧表面上的一个部分和与选择栅极电隔离的另一部分，以及通过形成在存储栅极下方的ONO层的p阱。 在选择栅极的侧面上形成侧壁状的氧化硅，在存储栅的侧面形成侧壁状的二氧化硅层和二氧化硅层。 形成在存储器栅下方的ONO层终止在氧化硅的下方，并且防止在沉积二氧化硅层期间在存储栅的端部附近的硅氧化物中产生低的击穿电压区域。

公开(公告)号：US07245531B2

公开(公告)日：2007-07-17

申请号：US11198191

申请日：2005-08-08

申请人： Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

发明人： Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

IPC分类号： G11C11/34

CPC分类号： H01L27/1157 ,  G11C16/0425 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

摘要： Memory cells are disposed in plural array form. Select gate electrodes of the memory cells arranged in an X direction are connected to one another by select gate lines respectively. Memory gate electrodes are connected by memory gate lines respectively. The memory gate lines respectively connected to the memory gate electrodes of the memory cells adjacent to one another through source regions interposed therebetween are not electrically connected to one another. Each of the select gate lines has a first portion that extends in the X direction, and a second portion 9b of which one end is connected to the first portion and extends in a Y direction. The memory gate line is formed on its corresponding sidewall of the select gate line with an insulating film interposed therebetween. The memory gate line has a contact section that extends in the X direction from over a second portion of the select gate line to over an element isolation region, and is connected to its corresponding wiring through a plug that buries a contact hole formed over the contact section.

摘要翻译： 存储单元以多个阵列形式布置。 选择沿X方向布置的存储单元的选择栅电极分别通过选择栅极线彼此连接。 存储器栅极电极分别由存储器栅极线连接。 分别连接到彼此相邻的存储单元的存储器栅极的存储栅极线通过其间的源极区域彼此不电连接。 每个选择栅极线具有在X方向上延伸的第一部分和其一端连接到第一部分并沿Y方向延伸的第二部分9b。 存储栅极线在其选择栅线的相应侧壁上形成有介于其间的绝缘膜。 存储栅极线具有接触部分，该接触部分在选择栅极线的第二部分上方在X方向上延伸到元件隔离区域上方，并且通过塞子连接到其对应的布线，所述插头埋设形成在触点上的接触孔 部分。