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    Prefetching data in a computer system
    41.
    发明申请
    Prefetching data in a computer system 有权
    在计算机系统中预取数据

    公开(公告)号：US20060117145A1

    公开(公告)日：2006-06-01

    申请号：US11331658

    申请日：2006-01-12

    Applicant: Eric Sprangle ,  Anwar Rohillah

    Inventor： Eric Sprangle ,  Anwar Rohillah

    IPC: G06F12/00

    CPC classification number: G06F12/0897 ,  G06F12/0862

    Abstract: A method and apparatus to detect and filter out redundant cache line addresses in a prefetch input queue, and to adjust the detector window size dynamically according to the number of detector entries in the queue for the cache-to-memory controller bus. Detectors correspond to cache line addresses that may represent cache misses in various levels of cache memory.

    Abstract translation: 一种用于检测和过滤预取输入队列中的冗余高速缓存行地址的方法和装置，并且根据用于高速缓存到存储器控制器总线的队列中的检测器条目的数量动态地调整检测器窗口大小。 检测器对应于高速缓存行地址，这可能代表各级高速缓存中的高速缓存未命中。

    Method and apparatus for determining a dynamic random access memory page management implementation
    42.
    发明申请
    Method and apparatus for determining a dynamic random access memory page management implementation 有权

    公开(公告)号：US20060112255A1

    公开(公告)日：2006-05-25

    申请号：US11323598

    申请日：2005-12-30

    Applicant: Eric Sprangle ,  Anwar Rohillah

    Inventor： Eric Sprangle ,  Anwar Rohillah

    IPC: G06F12/02

    CPC classification number: G06F13/1631 ,  G06F12/0215

    Abstract: A system and method for a processor to determine a memory page management implementation used by a memory controller without necessarily having direct access to the circuits or registers of the memory controller is disclosed. In one embodiment, a matrix of counters correspond to potential page management implementations and numbers of pages per block. The counters may be incremented or decremented depending upon whether the corresponding page management implementations and numbers of pages predict a page boundary whenever a long access latency is observed. The counter with the largest value after a period of time may correspond to the actual page management implementation and number of pages per block.

    MECHANISM FOR EFFECTIVELY CACHING STREAMING AND NON-STREAMING DATA PATTERNS
    49.
    发明申请
    MECHANISM FOR EFFECTIVELY CACHING STREAMING AND NON-STREAMING DATA PATTERNS 有权
    有效的高速缓存和非流动数据模式的机制

    公开(公告)号：US20110099333A1

    公开(公告)日：2011-04-28

    申请号：US12908183

    申请日：2010-10-20

    Applicant: Eric Sprangle ,  Anwar Rohillah ,  Robert Cavin

    Inventor： Eric Sprangle ,  Anwar Rohillah ,  Robert Cavin

    IPC: G06F12/12

    CPC classification number: G06F12/127 ,  G06F12/0862 ,  G06F12/124 ,  G06F2212/6028

    Abstract: A method and apparatus for efficiently caching streaming and non-streaming data is described herein. Software, such as a compiler, identifies last use streaming instructions/operations that are the last instruction/operation to access streaming data for a number of instructions or an amount of time. As a result of performing an access to a cache line for a last use instruction/operation, the cache line is updated to a streaming data no longer needed (SDN) state. When control logic is to determine a cache line to be replaced, a modified Least Recently Used (LRU) algorithm is biased to select SDN state lines first to replace no longer needed streaming data.

    Abstract translation: 本文描述了用于有效地高速缓存流和非流数据的方法和装置。 诸如编译器的软件识别最后使用的流指令/操作，这些指令/操作是用于访问多个指令或一定时间量的最后指令/操作来访问流数据。 作为执行对最后使用指令/操作的高速缓存线的访问的结果，将高速缓存行更新为不再需要的流数据（SDN）状态。 当控制逻辑要确定要替换的高速缓存行时，修改的最近最少使用（LRU）算法被偏置以首先选择SDN状态行来替换不再需要的流数据。

    MECHANISM FOR EFFECTIVELY HANDLING TEXTURE SAMPLING
    50.
    发明申请
    MECHANISM FOR EFFECTIVELY HANDLING TEXTURE SAMPLING 有权
    有效处理纹理抽样的机制

    公开(公告)号：US20090174721A1

    公开(公告)日：2009-07-09

    申请号：US11967408

    申请日：2007-12-31

    Applicant: Eric Sprangle

    Inventor： Eric Sprangle

    IPC: G09G5/00

    CPC classification number: G09G5/00 ,  G06F8/41 ,  G06T15/005 ,  G06T15/04 ,  G06T2200/28 ,  G09G5/026 ,  G09G2340/10 ,  G09G2360/121

    Abstract: A method and apparatus for efficiently handling texture sampling is described herein. A compiler or other software is capable of breaking a texture sampling operation for a pixel into a pre-fetch operation and a use operation. A processing element, in response to executing the pre-fetch operation, delegates computation of the texture sample of the pixel to a hardware texture sample unit. In parallel to the hardware texture sample unit performing a texture sample for the pixel and providing the result, i.e. a textured pixel (texel), to a destination address, the processing element is capable of executing other independent code. After an amount of time, the processing element executes the use operation, such as a load operation to load the texel from the destination address.

    Abstract translation: 本文描述了一种用于有效处理纹理采样的方法和装置。 编译器或其他软件能够将像素的纹理采样操作分解成预取操作和使用操作。 响应于执行预取操作，处理元件将像素的纹理样本的计算委托给硬件纹理采样单元。 与硬件纹理采样单元平行地执行像素的纹理样本并将结果（即，纹理像素（纹素））提供给目的地址，处理元件能够执行其他独立代码。 在一段时间之后，处理元件执行使用操作，例如从目的地地址加载纹素的加载操作。

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