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公开(公告)号:US11742283B2
公开(公告)日:2023-08-29
申请号:US17139117
申请日:2020-12-31
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor: Kah Wee Gan , Benfu Lin , Yun Ling Tan
IPC: H01L23/522 , H10B61/00 , H10N50/01 , H10N50/80 , H01L49/02
CPC classification number: H01L23/5228 , H01L28/20 , H10B61/00 , H10N50/01 , H10N50/80
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an integrated thin film resistor with a memory device and methods of manufacture. The structure includes a memory device in back end of line (BEOL) materials and a thin film resistor located in the BEOL materials. The thin film resistor includes electrical resistive material, and an insulator material over the electrical resistive material is thicker than insulator material over the memory device.
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公开(公告)号:US11728381B2
公开(公告)日:2023-08-15
申请号:US17238755
申请日:2021-04-23
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor: Kyongjin Hwang , Raunak Kumar , Robert J. Gauthier, Jr.
IPC: H01L29/10 , H01L29/66 , H01L27/02 , H01L29/735
CPC classification number: H01L29/1008 , H01L27/0259 , H01L27/0288 , H01L29/6625 , H01L29/735
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) devices and methods of manufacture. The structure includes a bipolar transistor device, including a base region, having a base contact region, in a first well of a first conductivity type, a collector region, having a collector contact region, in a second well of a second conductivity type, and an emitter region, having an emitter contact region, in the first well, located between the base contact region and the second well, and a reverse-doped resistance well, of the second conductivity type, located in the first well of the first conductivity type between the base contact region and the emitter contact region structured to decrease turn-on voltage of the bipolar transistor device.
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公开(公告)号:US20230255034A1
公开(公告)日:2023-08-10
申请号:US17650084
申请日:2022-02-07
Applicant: GlobalFoundries Singapore Pte. Ltd.
Inventor: DESMOND JIA JUN LOY , ENG HUAT TOH , SHYUE SENG TAN
CPC classification number: H01L27/2472 , H01L45/08 , H01L45/1226 , H01L45/1253 , H01L45/16
Abstract: The disclosed subject matter relates generally to structures, memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices having two resistive layers and a conductive layer arranged between two electrodes. The present disclosure provides a memory device including a first electrode above an interlayer dielectric region, a second electrode above the interlayer dielectric region, the second electrode is laterally adjacent to the first electrode, a conductive layer between the first electrode and the second electrode, in which the conductive layer is electrically isolated, a first resistive layer between the first electrode and the conductive layer, and a second resistive layer between the second electrode and the conductive layer.
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公开(公告)号:US11716914B2
公开(公告)日:2023-08-01
申请号:US17094819
申请日:2020-11-11
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor: Jianxun Sun , Juan Boon Tan , Tupei Chen
CPC classification number: H10N70/841 , H10B63/00 , H10N70/021 , H10N70/063
Abstract: A memory device and method of making the same is provided. The memory device comprises a first electrode having a length along a first axis, a second electrode having a length along a second axis that is perpendicular to the first axis, and a switching layer adjacent to the first electrode. A portion of the switching layer is positioned between a first electrode edge and a second electrode portion. The cross-sections of the first and second electrodes may have a polygonal shape.
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公开(公告)号:US20230197776A1
公开(公告)日:2023-06-22
申请号:US17644626
申请日:2021-12-16
Applicant: GlobalFoundries Singapore Pte. Ltd.
Inventor: Bong Woong Mun , Wanbing Yi , Juan Boon Tan , Jeoung Mo Koo
IPC: H01L29/06 , H01L23/14 , H01L23/528 , H01L21/762
CPC classification number: H01L29/0649 , H01L23/147 , H01L23/528 , H01L21/76224
Abstract: A structure includes a galvanic isolation including a horizontal portion including a first redistribution layer (RDL) electrode in a first insulator layer, and a second RDL electrode in the first insulator layer laterally spaced from the first RDL electrode. An isolation break includes a trench defined in the first insulator layer between the first RDL electrode and the second RDL electrode, and at least one second insulator layer in the trench. The first insulator layer and the second insulator layer(s) are between the first RDL electrode and the second RDL electrode. The isolation may separate, for example, voltage domains having different voltage levels. A related method is also disclosed. The isolation may also include a vertical portion using the first RDL electrode and another electrode in a metal layer separated from the first RDL electrode by a plurality of interconnect dielectric layers.
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公开(公告)号:US20230197320A1
公开(公告)日:2023-06-22
申请号:US17554337
申请日:2021-12-17
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor: Yudi SETIAWAN , Handoko LINEWIH , Siow Lee CHWA
CPC classification number: H01C1/08 , H01C7/006 , H01C17/075 , H05K1/115 , H05K1/167 , H05K1/0206
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heat dissipating structures and methods of manufacture. The structure includes: a thin film resistor within a back end of the line structure; and a heat dissipating structure below the thin film resistor, the heat dissipating structure includes a top plate with a slotted configuration and being within the back end of the line structure.
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公开(公告)号:US11652069B2
公开(公告)日:2023-05-16
申请号:US17114894
申请日:2020-12-08
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor: Ranjan Rajoo , Frank G. Kuechenmeister , Dirk Breuer
CPC classification number: H01L23/562 , H01L21/78
Abstract: The present disclosure relates to semiconductor structures, and more particularly, to crackstop structures and methods of manufacture. The structure includes: a die matrix comprising a plurality of dies separated by at least one scribe lane; and a crackstop structure comprising at least one line within the at least one scribe lane between adjacent dies of the plurality of dies.
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公开(公告)号:US11646279B2
公开(公告)日:2023-05-09
申请号:US17184659
申请日:2021-02-25
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor: Xiaodong Li , Ramasamy Chockalingam , Juan Boon Tan
CPC classification number: H01L24/05 , H01L24/03 , H01L2224/0221 , H01L2224/0236 , H01L2224/02375 , H01L2224/02381 , H01L2224/04042 , H01L2224/05647
Abstract: A semiconductor structure may be provided, including a conductive pad, a slot arranged through the conductive pad, a passivation layer arranged over the conductive pad and a plurality of electrical interconnects arranged under the conductive pad. The conductive pad may include an electrically conductive material and the slot may include an electrically insulating material. The passivation layer may include an opening that may expose a portion of the conductive pad and the slot may be arranged laterally between the exposed portion of the conductive pad and the plurality of electrical interconnects.
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公开(公告)号:US11641789B2
公开(公告)日:2023-05-02
申请号:US17355260
申请日:2021-06-23
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor: Yi Jiang , Benfu Lin , Lup San Leong , Curtis Chun-I Hsieh , Wanbing Yi , Juan Boon Tan
Abstract: According to various embodiments, there is provided a memory cell. The memory cell may include a transistor, a dielectric member, an electrode and a contact member. The dielectric member may be disposed over the transistor. The electrode may be disposed over the dielectric member. The contact member has a first end and a second end opposite to the first end. The first end is disposed towards the transistor, and the second end is disposed towards the dielectric member. The contact member has a side surface extending from the first end to the second end. The second end may have a recessed end surface that has a section that slopes towards the side surface so as to form a tip with the side surface at the second end. The dielectric member may be disposed over the second end of the contact member and may include at least a portion disposed over the tip.
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公开(公告)号:US11641739B2
公开(公告)日:2023-05-02
申请号:US16889726
申请日:2020-06-01
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor: Yongshun Sun , Eng Huat Toh , Shyue Seng Tan , Xinshu Cai , Lanxiang Wang
IPC: H01L27/11558 , H01L27/11539 , H01L29/66
Abstract: A memory device is provided. The memory device includes an active region in a substrate, an electrically-isolated electrode, and a dielectric layer. The electrically-isolated electrode is disposed over the active region. The dielectric layer is disposed between the electrically-isolated electrode and the active region and has a first dielectric portion having a first thickness and a second dielectric portion having a second thickness.
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