公开(公告)号：US12074211B2

公开(公告)日：2024-08-27

申请号：US17872790

申请日：2022-07-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jagar Singh

IPC: H01L29/735 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/735 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bipolar transistors and methods of manufacture. The structure includes: an emitter in a semiconductor substrate; a collector in the semiconductor substrate; a base contact region in the semiconductor substrate and adjacent to the collector and the emitter; and a shallow trench isolation structure overlapping the base contact region and separating the base contact region from the emitter and the collector.

公开(公告)号：US20240282853A1

公开(公告)日：2024-08-22

申请号：US18111995

申请日：2023-02-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani PANDEY ,  Rajendran KRISHNASAMY ,  Chung Foong TAN

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/7825 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/66704

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a device with workfunction metal in a drift region and methods of manufacture. The structure includes: a gate structure having at least a first workfunction metal in a channel region and a second workfunction metal, which is different from the first workfunction metal, in a trench in a drift region; and a sidewall spacer adjacent to the gate structure within the trench in the drift region.

公开(公告)号：US20240282847A1

公开(公告)日：2024-08-22

申请号：US18111959

申请日：2023-02-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani PANDEY ,  Sagar Premnath KARALKAR ,  Rajendran KRISHNASAMY ,  Chung Foong TAN

IPC: H01L29/74 ,  H01L29/66

CPC classification number: H01L29/74 ,  H01L29/66363

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high performance silicon controlled rectifier (SCR) devices and methods of manufacture. The structure includes: a first well in a semiconductor substrate; a second well in the semiconductor substrate, adjacent to the first well; and a porous semiconductor region extending in the first well and the second well.

公开(公告)号：US20240273275A1

公开(公告)日：2024-08-15

申请号：US18169315

申请日：2023-02-15

Applicant: GlobalFoundries U.S. Inc.

Inventor： Manubhai Patel Jignesh ,  James A. Culp ,  Bradley A. Orner ,  Haritez Narisetty

IPC: G06F30/392 ,  G06F30/31

CPC classification number: G06F30/392 ,  G06F30/31 ,  G06F2111/20

Abstract: Disclosed are a process design kit (PDK) product and also a design system and a design method that employ the PDK product to layout IC designs including 3D IC designs. The PDK product includes a storage medium and a PDK, including a library of cells, stored thereon. The cells can include parameterized cells (pcells) representing various IC components. The pcells are parameter-customizable and one or more of the pcells are also layout configuration-customizable. Each parameter and layout configuration-customizable pcell includes customization script, which is executable by a processor in response to inputs specific to that pcell and which can cause the processor to place an instance of that pcell with customized parameters in a 3D IC layout according to a selected layout configuration option (e.g., a single-chip layout configuration option or a multi-chip layout configuration option).

公开(公告)号：US12051690B2

公开(公告)日：2024-07-30

申请号：US17523956

申请日：2021-11-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sagar Premnath Karalkar ,  Prantik Mahajan ,  Jie Zeng ,  Ajay Ajay ,  Milova Paul ,  Souvick Mitra

IPC: H01L27/02

CPC classification number: H01L27/0262

Abstract: Disclosed is a semiconductor structure including a semiconductor substrate (e.g., a P-substrate) and a symmetric BDSCR. The BDSCR includes, within the substrate, a first well (e.g., a low-doped deep Nwell) and, within the first well, symmetric side sections and a middle section positioned laterally between the side sections. Each side section includes: second and third wells (e.g., Pwells), where the third well is shallower than and has a higher conductivity level than the second well. Each middle section includes multiple floating wells including: two fourth wells (e.g., Nwells), which have a higher conductivity level than the first well, and a fifth well (e.g., another Pwell), which is positioned laterally between and shallower than the fourth wells. By incorporating the floating wells into the middle section, high current tolerance is improved.

公开(公告)号：US12051465B2

公开(公告)日：2024-07-30

申请号：US17812485

申请日：2022-07-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Chandrahasa Reddy Dinnipati ,  Bipul C. Paul ,  Ramesh Raghavan

IPC: G11C13/00 ,  G11C11/16

CPC classification number: G11C13/004 ,  G11C11/1673 ,  G11C2013/0054 ,  G11C2213/79

Abstract: Disclosed is a sense circuit with first and second branches connected to first and second inputs of an amplifier. The first branch includes series-connected first transistors between a voltage rail and a data line and a first node between two first transistors and connected to the first input. First transistors on either side of the first node receive corresponding gate bias voltages. The second branch includes series-connected second transistors between the voltage rail and a reference device and a second node between two second transistors and connected to the second input. One first transistor and one second transistor share a common control signal. The first and second branches independently and concurrently generate data and reference voltages on the first and second nodes and the difference between them is sensed by the amplifier. Also disclosed are a non-volatile memory structure incorporating the sense circuit and a method.

公开(公告)号：US20240250158A1

公开(公告)日：2024-07-25

申请号：US18438882

申请日：2024-02-12

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Judson R. Holt ,  Vibhor Jain ,  Alexander M. Derrickson

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7393 ,  H01L29/0649 ,  H01L29/66325

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base region; an emitter region on a first side of the extrinsic base region; a collector region on a second side of the extrinsic base region; and a gate structure comprising a gate oxide and a gate control in a same channel region as the extrinsic base region.

公开(公告)号：US20240250157A1

公开(公告)日：2024-07-25

申请号：US18099366

申请日：2023-01-20

Applicant: GlobalFoundries U.S. Inc.

Inventor： Uppili S. RAGHUNATHAN ,  Vibhor JAIN ,  Yves T. NGU ,  Johnatan A. KANTAROVSKY ,  Sebastian T. VENTRONE

IPC: H01L29/73 ,  H01L23/34 ,  H01L27/07 ,  H01L29/06 ,  H01L29/08 ,  H01L29/737

CPC classification number: H01L29/7302 ,  H01L23/345 ,  H01L27/075 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/737

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heater terminal contacts, methods of operation and methods of manufacture. The structure includes: a heterojunction bipolar transistor having a collector, sub-collector region, emitter and base region; and heater terminal contacts electrically coupled to the sub-collector region.

公开(公告)号：US20240250126A1

公开(公告)日：2024-07-25

申请号：US18098999

申请日：2023-01-19

Applicant: GlobalFoundries U.S. Inc.

Inventor： Francois Hebert

IPC: H01L29/16 ,  H01L21/02 ,  H01L21/033 ,  H01L21/3205 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1608 ,  H01L21/02244 ,  H01L21/0332 ,  H01L21/32053 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66666 ,  H01L29/7827

Abstract: Structures for a field-effect transistor and methods of forming such structures. The structure comprises a semiconductor substrate including a top surface, a doped region adjacent to the top surface, and a trench that extends through the doped region. The semiconductor substrate comprises a wide bandgap semiconductor material. The structure further comprises a gate structure including a gate conductor layer. The gate conductor layer has a first portion disposed above the top surface of the semiconductor substrate and a second portion disposed inside the trench below the top surface of the semiconductor substrate.

公开(公告)号：US20240249992A1

公开(公告)日：2024-07-25

申请号：US18099389

申请日：2023-01-20

Applicant: GlobalFoundries U.S. Inc.

Inventor： Uppili S. RAGHUNATHAN ,  Vibhor JAIN ,  Yves T. NGU ,  Johnatan A. KANTAROVSKY ,  Sebastian T. VENTRONE

IPC: H01L23/34 ,  H01L29/737

CPC classification number: H01L23/345 ,  H01L29/7371

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heater elements, methods of operation and methods of manufacture. The structure includes: an active device; a heater element under the active device and within a semiconductor substrate; and a contact to the heater element and the active device.