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41.发明授权Method and apparatus for determining jitter and pulse width from clock signal comparisons 失效用于从时钟信号比较确定抖动和脉冲宽度的方法和装置公开(公告)号：US07286947B1
公开(公告)日：2007-10-23
申请号：US11279651
申请日：2006-04-13
IPC分类号： G06F19/00
CPC分类号： G01R31/31709 , G01R31/31725
摘要： A method and apparatus for determining jitter and pulse width from clock signal comparisons provides a low cost and production-integrable mechanism for measuring a clock signal with a reference clock, both of unknown frequency. The measured clock signal is sampled at transitions of a reference clock and the sampled values are collected in a histogram according to a folding of the samples around a timebase which is either swept to detect a minimum jitter for the folded data or is obtained from direct frequency analysis for the sample set. The histogram for the correct estimated period is statistically analyzed to yield the pulse width, which is the difference between the peaks of the probability density function and jitter, which corresponds to width of the density function peaks. Frequency drift is corrected by adjusting the timebase used to fold the data across the sample set.
摘要翻译： 用于从时钟信号比较确定抖动和脉冲宽度的方法和装置提供了一种低成本和可生产可集成的机制，用于测量具有未知频率的参考时钟的时钟信号。 测量的时钟信号在参考时钟的转变时被采样，并且采样值被收集在直方图中，根据时基的周围样本的折叠，该时基被扫描以检测折叠数据的最小抖动，或者从直接频率获得 分析样本集。 统计分析正确估计周期的直方图以产生脉冲宽度，其是概率密度函数和抖动的峰值之间的差异，其对应于密度函数峰值的宽度。 通过调整用于将样本集合中的数据折叠的时基来校正频率漂移。
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42.发明授权Receiver for clock and data recovery and method for calibrating sampling phases in a receiver for clock and data recovery 失效用于时钟和数据恢复的接收器以及用于校准接收机中的采样相位以用于时钟和数据恢复的方法公开(公告)号：US07149269B2
公开(公告)日：2006-12-12
申请号：US10375286
申请日：2003-02-27
IPC分类号： H03D3/24
CPC分类号： H03L7/07 , H03L7/091 , H03L7/0998 , H04L7/0025 , H04L7/0337
摘要： A receiver for clock and data recovery includes n sampling latches (SL1 . . . SLn) for determining n sample values (SV1 . . . SVn) of a reference signal (Ref2) at n sampling phases (φ1a . . . (φna) having sampling latch inputs and sampling latch outputs. The receiver further includes a phase position analyzer (5) connected to the sampling latch outputs for generating an adjusting signal (AS) for adjusting the sampling phase (φ1a . . . φna), if the sample value (SV1 . . . SVn) deviates from a set point and a phase interpolator (9) for generating sampling phases (φ1u . . . φnu). A sampling phase adjusting unit (6) connected with its inputs to the phase position analyzer (5) and the phase interpolator (9) and with its outputs to the sampling latches (SL1 . . . SLn) is provided for generating adjusted sampling phases (φ1a . . . φna) depending on the sampling phases (φ1u . . . φnu) and said adjusting signal (AS).
摘要翻译： 用于时钟和数据恢复的接收机包括n个采样锁存器（SL1 ... SLn），用于确定n个采样相位（参见图1a）上的参考信号（Ref 2）的n个采样值（SV1 ... SVn）。 （phina）具有采样锁存输入和采样锁存输出，接收器还包括连接到采样锁存器输出的相位位置分析器（5），用于产生调整信号（AS），用于调整采样相位（phi 1 a。 如果采样值（SV1 ... SVn）偏离设定点，则产生采样相位（phi 1 u。。phinu）的相位插值器（9），连接的采样相位调整单元（6） 其相位位置分析器（5）和相位插值器（9）的输入及其对采样锁存器（SL1 ... SLn）的输出被提供用于产生经调整的采样相位（phi1，...） 取决于采样相位（phi 1 u。。phinu）和所述调整信号（AS）。
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43.发明授权Dynamic measurement of communication channel characteristics using direct sequence spread spectrum (DSSS) systems, methods and program products 失效使用直接序列扩频（DSSS）系统，方法和程序产品对通信信道特性的动态测量公开(公告)号：US07088766B2
公开(公告)日：2006-08-08
申请号：US10014455
申请日：2001-12-14
CPC分类号： H04B1/707 , H04B1/7095
摘要： A DSSS system determines transmission reliability of a communication channel in real time. A DSSS transmitter (f0=1/T) generates a Pseudo Noise (PN) code and modulates a carrier source [cos. (2Σγc)] with a selected chip rate. The transmitter bandwidth is a direct function of the chip rate. The PN coded carrier signal is further modulated by a data signal [m(t)] to provide an output signal [s(t)] to a correlator via a communication channel for purposes of determining the transmission characteristic of the channel. The correlator running a variable length pseudo noise code combines the code and the carrier which relates the incoming data signal to a correlation value for detecting the data signal. The correlation value is compared to a threshold value based upon experience of reliable transmission of data through the communication channel. The value of the correlation value declines as the data is attenuated in the communication channel, thus, the band limiting effect of the communication can be determined by the change in the correlation value.
摘要翻译： DSSS系统实时确定通信信道的传输可靠性。 DSSS发射机（f 0 0 = 1 / T）产生伪噪声（PN）码，并调制载波源[cos。 （2Sigmagamma c））]。 发射机带宽是芯片速率的直接函数。 PN编码的载波信号被数据信号[m（t）]进一步调制，以通过通信信道向相关器提供输出信号[s（t）]，以便确定信道的传输特性。 运行可变长度伪噪声码的相关器将代码和将输入数据信号相关联的载波组合成用于检测数据信号的相关值。 基于通过通信信道可靠地传输数据的经验将相关值与阈值进行比较。 在通信信道中数据被衰减时，相关值的值下降，因此通信的频带限制效果可以通过相关值的变化来确定。
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公开(公告)号：US06977558B2
公开(公告)日：2005-12-20
申请号：US10650396
申请日：2003-08-28
申请人： Hayden C. Cranford, Jr. , Stacy J. Garvin , Vernon R. Norman , Todd M. Rasmus , Peter R. Seidel
发明人： Hayden C. Cranford, Jr. , Stacy J. Garvin , Vernon R. Norman , Todd M. Rasmus , Peter R. Seidel
CPC分类号： H03L7/08 , H03L2207/06
摘要： A self-adaptive voltage regulator for a phase-locked loop is disclosed. The phase-locked loop includes a phase detector, a charge pump, a low pass filter, and a voltage control oscillator, wherein the low pass filter inputs a control voltage to a voltage controlled oscillator for generation of an output clock. According to the method and system disclosed herein, the self-adaptive voltage regulator is coupled to an output of the low pass filter for sensing the control voltage during normal operation of the phase-locked loop, and for dynamically adjusting the supply voltage, which is input to the voltage controlled oscillator in response to the control voltage, such that the phase-locked loop maintains the control voltage within a predefined range of a reference voltage.
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公开(公告)号：US4638464A
公开(公告)日：1987-01-20
申请号：US551450
申请日：1983-11-14
IPC分类号： H01L27/10 , G11C5/00 , G11C5/14 , G11C11/407 , G11C14/00 , G11C16/06 , G11C17/00 , H01L21/822 , H01L21/8247 , H01L27/04 , H01L29/788 , H01L29/792 , H02M3/07 , G11C11/24
摘要： A voltage generating system provides a plurality of different voltages for powering a dynamic nonvolatile random access memory (NVRAM) chip. The voltage generating system includes a pair of charge pumps. Each charge pump is coupled to a controller that senses the voltage level at the output of the charge pump and generates an enabling signal when said voltage is at a predetermined value. The signal activates a power down circuit which adjusts the charge pump output to a desired voltage level. A programmable oscillator provides the clocking signals for the controller. The charge pumps and programmable oscillators are periodically deactivated. As a result, the overall power consumption of the chip is reduced.
摘要翻译： 电压产生系统提供多个不同的电压来为动态非易失性随机存取存储器（NVRAM）芯片供电。 电压发生系统包括一对电荷泵。 每个电荷泵耦合到控制器，该控制器感测电荷泵的输出端的电压电平，并且当所述电压处于预定值时产生使能信号。 该信号激活一个将电荷泵输出调节到所需电压电平的掉电电路。 可编程振荡器为控制器提供时钟信号。 定时停用电荷泵和可编程振荡器。 结果，芯片的总功耗降低。
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46.发明授权
公开(公告)号：US4536720A
公开(公告)日：1985-08-20
申请号：US551451
申请日：1983-11-14
IPC分类号： H01L27/10 , G11C11/407 , H01L21/822 , H01L21/8247 , H01L27/04 , H01L29/788 , H01L29/792 , H03K3/03 , H03K3/354 , H03K3/70
CPC分类号： H03K3/354 , H03K3/0315 , H03K3/70
摘要： A programmable oscillator is provided for use on an integrated circuit chip. The oscillator includes a plurality of inverter delay stages connected in tandem between an input and an output node. A single FET device couples a node common to all of the inverter delay stages to a ground potential. Another FET device controls the input node. When a logic enabling signal is appropriately applied to the FET devices, the oscillator is controlled so that internal nodes of the oscillator float high when it is off and no energy is dissipated. In addition, the amount of delays between the delay stages and the input stage of the load is such that the load supplies the greater ratio of delays. This ensures that the oscillator's frequency of oscillation tracks the switching speed of the load.
摘要翻译： 提供了一种用于集成电路芯片的可编程振荡器。 该振荡器包括串联连接在输入和输出节点之间的多个反相器延迟级。 单个FET器件将所有反相器延迟级公共的节点耦合到地电位。 另一个FET器件控制输入节点。 当逻辑使能信号被适当地施加到FET器件时，振荡器被控制，使得振荡器的内部节点在关闭时浮起，并且没有能量消耗。 此外，延迟级与负载的输入级之间的延迟量使得负载提供较大的延迟比。 这确保振荡器的振荡频率跟踪负载的切换速度。
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公开(公告)号：US4429237A
公开(公告)日：1984-01-31
申请号：US245802
申请日：1981-03-20
IPC分类号： H01L21/8236 , H01L27/088 , H01L29/06 , H01L29/40 , H01L29/417 , H01L29/78 , H03K17/10 , H03K17/687 , H03K19/0944
CPC分类号： H01L29/402 , H01L29/41775 , H01L29/7838 , H03K17/102 , H03K19/09443
摘要： High voltage tolerant FET circuits are characterized by the use of shield structures surrounding source/drain diffusion pockets, with the shields tied to apropriate potentials, which in some cases is the associated gate potential. Some embodiments use enhancement mode devices which however have implanted channels underlying the shield structures. Operation of several embodiments is achieved near the snap-back limits by the use of a clamp to maintain potential drop below this limit. High voltage switching at heavy loads is achieved by a voltage divider providing appropriate gate potentials to the load carrying FETs.
摘要翻译： 高耐压FET电路的特征在于使用围绕源极/漏极扩散穴的屏蔽结构，其中屏蔽层被绑定到合适的电势，这在某些情况下是相关联的栅极电位。 一些实施例使用增强模式设备，然而其具有在屏蔽结构下方的植入通道。 几个实施例的操作通过使用夹具保持潜在的下降到该极限以下而在快速恢复极限附近实现。 重负载下的高电压开关是通过分压器为负载负载FET提供适当的栅极电压来实现的。
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公开(公告)号：US20130221987A1
公开(公告)日：2013-08-29
申请号：US13407822
申请日：2012-02-29
IPC分类号： G01R29/26
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/0409 , G11C2029/5002
摘要： A monitoring circuit and method, wherein a voltage waveform having a linear falling edge is applied to a first node of at least one test memory cell (e.g., a plurality of test memory cells connected in parallel). The input voltage at the first node is captured when the output voltage at a second node of the test memory cell(s) rises above a high reference voltage during the falling edge. Then, a difference is determined between the input voltage as captured and either (1) the output voltage at the second node, as captured when the input voltage at the first node falls below the first reference voltage during the falling edge, or (2) a low reference voltage. This difference is proportional to the static noise margin (SNM) of the test memory cell(s) such that any changes in the difference noted with repeated monitoring are indicative of corresponding changes in the SNM.
摘要翻译： 一种监视电路和方法，其中具有线性下降沿的电压波形被施加到至少一个测试存储器单元（例如，并联连接的多个测试存储单元）的第一节点。 当在下降沿期间，当测试存储单元的第二个节点处的输出电压上升到高于参考电压时，捕获第一节点处的输入电压。 然后，在捕获的输入电压和（1）第二节点处的输出电压之间确定差异，如在第一节点处的输入电压在下降沿期间低于第一参考电压时捕获的，或者（2） 低参考电压。 该差异与测试存储器单元的静态噪声容限（SNM）成比例，使得通过重复监测指出的差异中的任何变化表示SNM的相应变化。
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公开(公告)号：US08016482B2
公开(公告)日：2011-09-13
申请号：US11780530
申请日：2007-07-20
申请人： Igor Arsovski , Anthony R. Bonaccio , Serafino Bueti , Hayden C. Cranford, Jr. , Joseph A. Iandanza , Todd E. Leonard , Hemen R. Shah , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Igor Arsovski , Anthony R. Bonaccio , Serafino Bueti , Hayden C. Cranford, Jr. , Joseph A. Iandanza , Todd E. Leonard , Hemen R. Shah , Pradeep Thiagarajan , Sebastian T. Ventrone
CPC分类号： G05D23/20 , G05D23/1934
摘要： Method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating element therefor; a processing unit including: a comparator for comparing the temperature against a predetermined temperature value, a controller, which in the case that the temperature is below the predetermined temperature value, delays functional operation of the IC and controls heating of the region of the IC, and a monitor for monitoring the temperature in the region; and wherein the controller, in the case that the temperature rises above the predetermined temperature value, ceases the heating and initiates functional operation of the IC.
摘要翻译： 公开了对集成电路（IC）供电的方法和系统。 在一个实施例中，该系统包括IC中的包括功能逻辑的区域，用于感测IC上电时该区域中的温度的温度传感器及其加热元件; 处理单元，包括：用于将温度与预定温度值进行比较的比较器，在温度低于预定温度值的情况下的控制器，延迟IC的功能操作并控制IC的区域的加热， 以及监测该区域的温度的监测器; 并且其中所述控制器在所述温度升高到所述预定温度值以上的情况下停止所述加热并且启动所述IC的功能操作。
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公开(公告)号：US07936208B2
公开(公告)日：2011-05-03
申请号：US12184148
申请日：2008-07-31
申请人： Steven Mark Clements , Hayden C. Cranford, Jr. , Amar Chandra Mahadeo Dwarka , John Farley Ewen
发明人： Steven Mark Clements , Hayden C. Cranford, Jr. , Amar Chandra Mahadeo Dwarka , John Farley Ewen
IPC分类号： G05F3/02
CPC分类号： G05F3/205
摘要： A method and circuit for providing a bias voltage to a MOS device is disclosed. The method and circuit comprise utilizing at least one diode connected circuit to provide a voltage that tracks process, voltage and temperature variations of a semiconductor device. The method and circuit includes utilizing a current mirror circuit coupled to the at least one diode connected circuit to generate a bias voltage for the body of the semiconductor device from the voltage. The bias voltage allows for compensation for the process, voltage and temperature variations.
摘要翻译： 公开了一种用于向MOS器件提供偏置电压的方法和电路。 该方法和电路包括利用至少一个二极管连接的电路来提供跟踪半导体器件的工艺，电压和温度变化的电压。 所述方法和电路包括利用耦合到所述至少一个二极管连接的电路的电流镜电路，以从所述电压产生所述半导体器件的主体的偏置电压。 偏置电压允许对过程，电压和温度变化进行补偿。
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