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    MULTILAYER CERAMIC CONDENSER AND METHOD OF MANUFACTURING THE SAME
    43.
    发明申请
    MULTILAYER CERAMIC CONDENSER AND METHOD OF MANUFACTURING THE SAME 有权
    多层陶瓷冷凝器及其制造方法

    公开(公告)号：US20120147522A1

    公开(公告)日：2012-06-14

    申请号：US13276752

    申请日：2011-10-19

    Applicant: Hyung Joon KIM ,  Jong Hoon Kim

    Inventor： Hyung Joon KIM ,  Jong Hoon Kim

    IPC: H01G4/12 ,  H01G7/00

    CPC classification number: H01G4/0085 ,  H01G4/12 ,  H01G4/30 ,  Y10T29/43

    Abstract: Disclosed are a multilayer ceramic condenser and a method of manufacturing a multilayer ceramic condenser. There is provided a method of manufacturing a multilayer ceramic condenser, including: printing a plurality of stripe-type inner electrode patterns on a ceramic green sheet in parallel; forming a laminate by stacking ceramic green sheets on which a plurality of stripe-type inner electrode patterns are formed; cutting the laminate so that a first inner electrode pattern and a second inner electrode pattern are alternately stacked; and forming a first side part and a second side part by applying ceramic slurry in order to cover the side of the laminate to which both the first inner electrode pattern and the second inner electrode pattern are exposed.

    Abstract translation: 公开了一种多层陶瓷冷凝器和制造多层陶瓷冷凝器的方法。 提供一种制造多层陶瓷冷凝器的方法，包括：平行地在陶瓷生片上印刷多个条状内部电极图案; 通过堆叠形成多个条形内部电极图案的陶瓷生片来形成层压体; 切割层压体，使得第一内部电极图案和第二内部电极图案交替堆叠; 以及通过施加陶瓷浆料形成第一侧面部分和第二侧面部分，以覆盖第一内部电极图案和第二内部电极图案两者都露出的层压体的一侧。

    Liquid crystal display
    44.
    发明授权
    Liquid crystal display 有权
    液晶显示器

    公开(公告)号：US08144113B2

    公开(公告)日：2012-03-27

    申请号：US12314806

    申请日：2008-12-17

    Applicant: Joon Kyu Park ,  Jong Hoon Kim

    Inventor： Joon Kyu Park ,  Jong Hoon Kim

    IPC: G09G3/36

    CPC classification number: G09G3/342 ,  G09G2320/064 ,  G09G2320/0646 ,  G09G2330/021 ,  G09G2360/16

    Abstract: Disclosed herein is a liquid crystal display capable of reducing a side effect during local LED dimming to reduce power consumption and improve display quality. The liquid crystal display includes a liquid crystal panel having a plurality of liquid crystal cells formed respectively in a plurality of pixel areas defined by intersections of a plurality of gate lines and a plurality of data lines, a data driver for supplying data voltages to the data lines, a gate driver for supplying scan signals to the gate lines, a timing controller for controlling the data driver and gate driver and outputting a plurality of dimming signals based on an average picture level (APL) detected based on video data supplied to the liquid crystal panel, and a light emitting diode (LED) backlight unit for partitioning the liquid crystal panel into a plurality of areas and supplying appropriate pulse width modulation (PWM) control signals based on the dimming signals to a plurality of LED arrays installed to correspond respectively to the partitioned areas, to supply light to the liquid crystal panel.

    Abstract translation: 这里公开了一种液晶显示器，其能够在局部LED调光期间减少副作用以降低功耗并提高显示质量。 液晶显示器包括具有分别形成在由多条栅极线和多条数据线的交点限定的多个像素区域中的多个液晶单元的液晶面板，用于向数据提供数据电压的数据驱动器 线路，用于向栅极线提供扫描信号的栅极驱动器，用于控制数据驱动器和栅极驱动器并基于基于提供给液体的视频数据检测到的平均图像电平（APL）输出多个调光信号的定时控制器 水晶面板和用于将液晶面板分割成多个区域的发光二极管（LED）背光单元，并且基于调光信号向安装的多个LED阵列提供适当的脉宽调制（PWM）控制信号，以分别对应 到分隔区域，以向液晶面板提供光。

    Data transmission system and method
    45.
    发明授权
    Data transmission system and method 失效
    数据传输系统及方法

    公开(公告)号：US08089860B2

    公开(公告)日：2012-01-03

    申请号：US11708557

    申请日：2007-02-21

    Applicant: Jong-Hoon Kim ,  Jae-Jun Lee ,  Kwang-Soo Park

    Inventor： Jong-Hoon Kim ,  Jae-Jun Lee ,  Kwang-Soo Park

    IPC: H04J7/00

    CPC classification number: H03M5/145

    Abstract: Data transmission system and method are provided. The transmission system includes a data converter and data restoring unit. The data converter converts N-bit first data to be transmitted into M-bit second data, where M is greater than N and the second data is arranged in a minimum unit greater than 1, each minimum unit including at least successive data bits having the same phase. The transmitter compresses the second data prior to transmission via a channel having performance characteristics defining a minimum pulse width, and a receiver receives and de-compresses the transmitted second data. The data restoring unit then restores the first data from the second.

    Abstract translation: 提供数据传输系统和方法。 传输系统包括数据转换器和数据恢复单元。 数据转换器将要发送的N位第一数据转换成M位第二数据，其中M大于N，第二数据以大于1的最小单位排列，每个最小单位包括至少连续的数据位， 相同阶段 发射机在通过具有定义最小脉冲宽度的性能特征的信道进行传输之前压缩第二数据，并且接收机接收和解压缩传输的第二数据。 数据恢复单元然后从第二数据恢复第一数据。

    Through-electrode, circuit board having a through-electrode, semiconductor package having a through-electrode, and stacked semiconductor package having the semiconductor chip or package having a through-electrode
    46.
    发明授权
    Through-electrode, circuit board having a through-electrode, semiconductor package having a through-electrode, and stacked semiconductor package having the semiconductor chip or package having a through-electrode 失效
    通孔电极，具有贯通电极的电路板，具有贯通电极的半导体封装，以及具有半导体芯片或封装的叠层半导体封装，具有贯通电极

    公开(公告)号：US08072046B2

    公开(公告)日：2011-12-06

    申请号：US12209584

    申请日：2008-09-12

    Applicant: Han Jun Bae ,  Jong Hoon Kim

    Inventor： Han Jun Bae ,  Jong Hoon Kim

    IPC: H01L23/538 ,  H05K1/02

    CPC classification number: H05K3/4046 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K2201/0347 ,  H05K2201/10242 ,  H01L2924/00

    Abstract: A stacked semiconductor package includes a first semiconductor package having a first semiconductor chip having a first pad and a through-hole passing through a the portion corresponding to the pad; a second semiconductor package disposed over the first semiconductor package, and including a second semiconductor chip having a second pad disposed at a portion corresponding to the first pad and blocking the through-hole; and a through-electrode disposed within the through-hole, and having a pillar shaped core supported by the second pad, a through-electrode unit disposed over a surface of the core and electrically connected with the second pad, a first metal layer interposed between the core and the through electrode unit, and a second metal layer interposed between an inner surface of the first semiconductor chip formed by the through-hole and the through-electrode unit.

    Abstract translation: 堆叠半导体封装包括具有第一半导体芯片的第一半导体封装，第一半导体芯片具有第一焊盘和穿过对应于焊盘的部分的通孔; 第二半导体封装，设置在所述第一半导体封装上，并且包括第二半导体芯片，所述第二半导体芯片具有设置在与所述第一焊盘对应的部分处并阻塞所述通孔的第二焊盘; 以及设置在所述通孔内的贯通电极，并具有由所述第二焊盘支撑的柱状芯，贯通电极单元，设置在所述芯的表面上并与所述第二焊盘电连接;第一金属层， 芯和贯通电极单元，以及插入在由通孔形成的第一半导体芯片的内表面和通孔单元之间的第二金属层。

    Semiconductor package and method for manufacturing the same
    47.
    发明授权
    Semiconductor package and method for manufacturing the same 有权
    半导体封装及其制造方法

    公开(公告)号：US08049341B2

    公开(公告)日：2011-11-01

    申请号：US12244322

    申请日：2008-10-02

    Applicant: Seung Taek Yang ,  Min Suk Suh ,  Seung Hyun Lee ,  Jong Hoon Kim

    Inventor： Seung Taek Yang ,  Min Suk Suh ,  Seung Hyun Lee ,  Jong Hoon Kim

    IPC: H01L23/52

    CPC classification number: H01L23/481 ,  H01L23/3128 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05099

    Abstract: A stacked semiconductor package and a method for manufacturing the same are presented which exhibit a reduced electrical resistance and an increased junction force. The semiconductor package includes at least two semiconductor chips stacked upon each other. Each semiconductor chip has a plurality of bonding pads formed on upper surfaces and has via-holes. First wiring lines are located on the upper surfaces of the semiconductor chips, on the surfaces of the via-holes, and respectively connected onto their respective bonding pads. Second wiring lines are located on lower surfaces of the semiconductor chips and on the surfaces of the respective via-holes which connect to their respective first wiring lines. The semiconductor chips are stacked so that the first wiring lines on an upper surface of an upwardly positioned semiconductor chip are respectively joined with corresponding second wiring lines formed on a lower surface of a downwardly positioned semiconductor chip.

    Abstract translation: 本发明提供一种叠层半导体封装及其制造方法，其具有降低的电阻和增加的接合力。 半导体封装包括彼此堆叠的至少两个半导体芯片。 每个半导体芯片具有形成在上表面上并具有通孔的多个接合焊盘。 第一布线位于半导体芯片的上表面上，位于通孔的表面上，分别连接到它们各自的接合焊盘上。 第二布线位于半导体芯片的下表面和连接到它们各自的第一布线的相应通孔的表面上。 半导体芯片被堆叠，使得位于向上定位的半导体芯片的上表面上的第一布线分别与形成在向下定位的半导体芯片的下表面上的相应的第二布线接合。

    SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR MEMORY MODULE AND SEMICONDUCTOR MEMORY SYSTEM INCLUDING THE SEMICONDUCTOR MEMORY DEVICE
    48.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR MEMORY MODULE AND SEMICONDUCTOR MEMORY SYSTEM INCLUDING THE SEMICONDUCTOR MEMORY DEVICE 失效
    半导体存储器件，半导体存储器模块和半导体存储器系统，包括半导体存储器件

    公开(公告)号：US20110110168A1

    公开(公告)日：2011-05-12

    申请号：US12833444

    申请日：2010-07-09

    Applicant: Myung-hee Sung ,  Jong-hoon Kim

    Inventor： Myung-hee Sung ,  Jong-hoon Kim

    IPC: G11C5/14 ,  G11C7/00

    CPC classification number: G11C7/02 ,  G11C5/04

    Abstract: A semiconductor memory device, a semiconductor memory module, and a semiconductor memory system including the same, the semiconductor memory device including a command/address input buffer that receives a command/address signal and a command/address reference voltage signal, wherein the command/address input buffer is configured to amplify a difference between the command/address signal and the command/address reference voltage signal, and is further configured to output the amplified difference between the command/address signal and the command/address reference voltage signal, and a chip selection input buffer that receives a chip selection signal and a chip selection reference voltage signal, wherein the chip selection input buffer is configured to amplify a difference between the chip selection signal and the chip selection reference voltage signal, and is further configured to output the amplified difference between the chip selection signal and the chip selection reference voltage signal, wherein a voltage level of the command/address reference voltage signal is different from a voltage level of the chip selection reference voltage signal.

    Abstract translation: 半导体存储器件，半导体存储器模块和包括该半导体存储器模块的半导体存储器系统，该半导体存储器件包括接收命令/地址信号的命令/地址输入缓冲器和命令/地址参考电压信号，其中命令/ 地址输入缓冲器被配置为放大命令/地址信号和命令/地址参考电压信号之间的差，并且还被配置为输出指令/地址信号和命令/地址参考电压信号之间的放大差值，以及 接收芯片选择信号的芯片选择输入缓冲器和芯片选择基准电压信号，其中芯片选择输入缓冲器被配置为放大芯片选择信号和芯片选择参考电压信号之间的差异，并且还被配置为输出 芯片选择信号与芯片选择参考电压之间的放大差异 e信号，其中指令/地址参考电压信号的电压电平不同于芯片选择基准电压信号的电压电平。

    Case for portable electronic device
    49.
    发明授权
    Case for portable electronic device 失效
    便携式电子设备案例

    公开(公告)号：US07921996B2

    公开(公告)日：2011-04-12

    申请号：US11644111

    申请日：2006-12-22

    Applicant: Jong-weon Seo ,  Jong-hoon Kim ,  Chang-sik Kim ,  Sang-moon Lee ,  Jeong-bae Kim

    Inventor： Jong-weon Seo ,  Jong-hoon Kim ,  Chang-sik Kim ,  Sang-moon Lee ,  Jeong-bae Kim

    IPC: B65D85/00

    CPC classification number: H05K5/0204

    Abstract: Provided is a case for a portable electronic device. The case includes an outer part; an inner part coupled to an inner surface of the outer part and including a plurality of holes; and fastening members, each including a main body having an outer diameter corresponding to an inner diameter of the hole in the inner part and a flange portion, wherein the flange portion is connected to an end portion of the main body, has an outer diameter greater than the outer diameter of the main body to be depressed into the inner part.

    Abstract translation: 提供了一种用于便携式电子设备的情况。 案件包括外部部分; 内部部分，其耦合到所述外部部件的内表面并且包括多个孔; 以及紧固构件，每个紧固构件包括具有与内部的孔的内径相对应的外径的主体和凸缘部，其中所述凸缘部连接到所述主体的端部，所述外径更大 比主体的外径要被压入内部。

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