公开(公告)号：US08395953B2

公开(公告)日：2013-03-12

申请号：US12958726

申请日：2010-12-02

Applicant: Cheol Kim ,  Sang-Kyun Park ,  Jung-Bae Lee ,  Jun-Phyo Lee

Inventor： Cheol Kim ,  Sang-Kyun Park ,  Jung-Bae Lee ,  Jun-Phyo Lee

IPC: G11C7/00

CPC classification number: G11C11/4091 ,  G11C29/025 ,  G11C29/12005 ,  G11C29/1201 ,  G11C2029/1204

Abstract: The bit-line sense amplifier includes a driving-voltage control circuit and an amplifier. The driving-voltage control circuit generates a first test driving voltage having a voltage level of a pre-charge voltage, a second test driving voltage having a voltage level of a pre-charge voltage added by a voltage difference between a bit-line and a complementary bit-line, and a third test driving voltage having a voltage level of a pre-charge voltage subtracted by the voltage difference in a test mode. The amplifier senses and amplifies a voltage difference between the bit-line and the complementary bit-line.

Abstract translation: 位线读出放大器包括驱动电压控制电路和放大器。 驱动电压控制电路产生具有预充电电压的电压电平的第一测试驱动电压，具有由位线和位线之间的电压差相加的预充电电压的电压电平的第二测试驱动电压 以及第三测试驱动电压，其具有在测试模式下被电压差减去的预充电电压的电压电平。 放大器感测并放大位线和互补位线之间的电压差。

公开(公告)号：US08391095B2

公开(公告)日：2013-03-05

申请号：US12768060

申请日：2010-04-27

Applicant: Ho-Cheol Lee ,  Jung-Bae Lee

Inventor： Ho-Cheol Lee ,  Jung-Bae Lee

IPC: G11C5/14

CPC classification number: G11C5/148 ,  G11C5/144 ,  G11C5/147 ,  G11C8/16

Abstract: Disclosed is a method of controlling a deep power down mode in a multi-port semiconductor memory having a plurality of ports connected to a plurality of processors. Control of the deep power down mode in the multi-port semiconductor memory is performed such that activation/deactivation of the deep power down mode are determined in accordance with signals applied through various ports in the plurality of ports.

Abstract translation: 公开了一种在多端口半导体存储器中控制深度掉电模式的方法，该多端口半导体存储器具有连接到多个处理器的多个端口。 执行多端口半导体存储器中的深度掉电模式的控制，使得根据通过多个端口中的各个端口施加的信号来确定深度掉电模式的激活/去激活。

公开(公告)号：US08362539B2

公开(公告)日：2013-01-29

申请号：US12458874

申请日：2009-07-27

Applicant: Ki-Whan Song ,  Jung-Bae Lee

Inventor： Ki-Whan Song ,  Jung-Bae Lee

IPC: H01L27/108

CPC classification number: H01L23/481 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes a first substrate including at least one first well region and first impurity regions on portions of the substrate and a bias voltage plate on a surface of the substrate. A semiconductor device may be of a three dimensional stack structure, and in example embodiments, the semiconductor device may further include a through contact plug substantially perpendicularly penetrating at least one substrate and at least one bias voltage plate. Therefore, a design margin of a semiconductor device may be enhanced and a bias voltage may be provided reliably.

Abstract translation: 半导体器件包括：第一衬底，包括至少一个第一阱区域和衬底的部分上的第一杂质区域以及衬底表面上的偏压板。 半导体器件可以是三维堆叠结构，并且在示例性实施例中，半导体器件还可以包括基本垂直地穿透至少一个衬底和至少一个偏置电压板的贯穿接触插塞。 因此，可以提高半导体器件的设计裕度，并且可以可靠地提供偏置电压。

公开(公告)号：US08205135B2

公开(公告)日：2012-06-19

申请号：US13228763

申请日：2011-09-09

Applicant: Jung-Bae Lee

Inventor： Jung-Bae Lee

IPC: H03M13/00

CPC classification number: G06F11/1008

Abstract: A memory system including a memory controller and a memory and a related method are disclosed. The method includes communicating a command and error detection/correction (EDC) data associated with the command from the memory controller to the memory, decoding the command and executing an EDC operation related to the EDC data in parallel, and if the command is a write command, delaying execution of a write operation indicated by the write command until completion of the EDC operation, else immediately executing an operation indicated by the command without regard to completion of the EDC operation.

Abstract translation: 公开了一种包括存储器控制器和存储器以及相关方法的存储器系统。 该方法包括将与命令相关联的命令和错误检测/校正（EDC）数据从存储器控制器传送到存储器，解码该命令并并行执行与EDC数据相关的EDC操作，并且如果命令是写入 命令，延迟执行由写入命令指示的写入操作，直到完成EDC操作，否则立即执行由命令指示的操作，而不考虑完成EDC操作。

公开(公告)号：US08154934B2

公开(公告)日：2012-04-10

申请号：US12788029

申请日：2010-05-26

Applicant: Ho-Young Kim ,  Ho-Cheol Lee ,  Jung-Bae Lee

Inventor： Ho-Young Kim ,  Ho-Cheol Lee ,  Jung-Bae Lee

IPC: G11C7/00 ,  G11C8/18

CPC classification number: G11C7/22 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/222 ,  G11C2207/2272

Abstract: A semiconductor memory device is disclosed. The semiconductor device includes a memory cell array, a clock signal generator configured to receive an external clock signal from the outside of the memory device and output an internal clock signal, and a data output unit configured to receive an internal data signal from the memory cell array and output a read data signal in response to the internal clock signal. The semiconductor memory device also includes a read data strobe unit configured to output a read data strobe signal having a cycle time of n times (n is an integer equal to or more than 2) a cycle time of the internal clock signal, based on the internal clock signal.

Abstract translation: 公开了一种半导体存储器件。 半导体器件包括存储单元阵列，时钟信号发生器，被配置为从存储器件的外部接收外部时钟信号并输出​​内部时钟信号;以及数据输出单元，被配置为从存储器单元接收内部数据信号 阵列并响应于内部时钟信号输出读取数据信号。 半导体存储器件还包括读取数据选通单元，其被配置为基于内部时钟信号的周期时间，输出具有n倍（n是等于或大于2的整数）的周期时间的读取数据选通信号 内部时钟信号。

公开(公告)号：US20110314349A1

公开(公告)日：2011-12-22

申请号：US13221418

申请日：2011-08-30

Applicant: Jung-Bae LEE

Inventor： Jung-Bae LEE

IPC: H04L1/18

CPC classification number: H04L1/1671 ,  H04L1/0025 ,  H04L25/0272 ,  H04L25/0278 ,  H04L25/0288 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03885

Abstract: A system having a transmission unit transmitting an output data signal formed from output data and related error detection code and a corresponding receiving unit. The output data signal is pre-emphasized by a pre-emphasis driver in the transmission unit. The receiving unit includes an equalizer equalizing the received output data signal and an error detector analyzing the error detection code to determine whether a bit error is present in the received data. Upon successive data transmission failures either an equalization coefficient in the equalizer or a pre-emphasis coefficient in the pre-emphasis driver are changed.

Abstract translation: 一种具有发送单元的系统，该发送单元发送由输出数据和相关错误检测码形成的输出数据信号和相应的接收单元。 输出数据信号由传输单元中的预加重驱动器预先强调。 接收单元包括均衡接收的输出数据信号的均衡器和分析错误检测码的误差检测器，以确定接收数据中是否存在位错误。 在连续数据传输故障时，均衡器中的均衡系数或预加重驱动器中的预加重系数被改变。

公开(公告)号：US08050332B2

公开(公告)日：2011-11-01

申请号：US12103823

申请日：2008-04-16

Applicant: Hoe-ju Chung ,  Jung-bae Lee

Inventor： Hoe-ju Chung ,  Jung-bae Lee

IPC: H04B14/06

CPC classification number: H04L25/0264 ,  H04L25/0272

Abstract: In a communication system, data is selectively transmitted using single-ended or differential signaling. The data is transmitted in relation to a plurality of clock signals having different relative phases. When the data is transmitted using single-ended signaling, data on adjacent signal lines undergo logic transitions at different times in relation to the plurality of clock signals.

Abstract translation: 在通信系统中，使用单端或差分信令有选择地发送数据。 相对于具有不同相对相位的多个时钟信号发送数据。 当使用单端信令发送数据时，相邻信号线上的数据相对于多个时钟信号在不同时刻进行逻辑转换。

公开(公告)号：US07999367B2

公开(公告)日：2011-08-16

申请号：US12123583

申请日：2008-05-20

Applicant: Uk-song Kang ,  Jung-bae Lee ,  Hoe-ju Chung

Inventor： Uk-song Kang ,  Jung-bae Lee ,  Hoe-ju Chung

IPC: H01L23/02

CPC classification number: G11C5/025 ,  G11C5/02 ,  G11C5/063 ,  H01L25/0657 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/15331 ,  H01L2224/05599

Abstract: A semiconductor memory device includes a stacked plurality of interposer chips, each interposer chip seating a smaller corresponding memory chip, wherein a lowermost interposer chip in the stacked plurality of interposer chips is mounted on a buffer chip. Each one of the stacked plurality of interposer chips includes a central portion having bond pads seating the corresponding memory device and a peripheral portion having a plurality of through silicon vias (TSVs). The respective pluralities of TSVs for adjacent interposer chips in the stacked plurality of interposer chips are connected via vertical connection elements to form multiple internal signal paths communicating write data from and read data to the buffer chip from respective memory chips.

Abstract translation: 半导体存储器件包括堆叠的多个插入器芯片，每个插入器芯片放置较小的对应的存储器芯片，其中堆叠的多个插入器芯片中的最下层插入器芯片安装在缓冲芯片上。 堆叠的多个插入器芯片中的每一个包括具有连接衬垫对应的存储器件的中心部分和具有多个穿通硅通孔（TSV）的外围部分。 堆叠的多个插入器芯片中的相邻插入器芯片的相应多个TSV通过垂直连接元件连接，以形成从相应存储器芯片向缓冲器芯片传送写入数据和从其读取数据的多个内部信号路径。

公开(公告)号：US07996590B2

公开(公告)日：2011-08-09

申请号：US12539840

申请日：2009-08-12

Applicant: Jung-bae Lee

Inventor： Jung-bae Lee

IPC: G06F13/00 ,  H03K17/16 ,  H03K19/003

CPC classification number: G11C5/04 ,  G11C5/06 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C11/409

Abstract: A semiconductor memory module includes a memory module board having at least one semiconductor memory device. The semiconductor memory device includes a data input buffer that receives data and a first reference voltage via first and second input terminals, a command/address buffer that receives a command/address signal and a second reference voltage via first and second input terminals, and a first termination resistor unit connected to the first input terminal of the data input buffer. The semiconductor memory module further includes a second termination resistor unit located on the memory module board and connected to an internal command/address bus. The first termination resistor unit includes a first resistor connected between a first voltage source and the first input terminal of the data input buffer, and the second termination resistor unit includes a second resistor connected between a second voltage source and the first input terminal of the command/address input buffer.

Abstract translation: 半导体存储器模块包括具有至少一个半导体存储器件的存储器模块板。 半导体存储器件包括经由第一和第二输入端子接收数据和第一参考电压的数据输入缓冲器，经由第一和第二输入端子接收命令/地址信号和第二参考电压的命令/地址缓冲器，以及 连接到数据输入缓冲器的第一输入端的第一终端电阻单元。 半导体存储器模块还包括位于存储器模块板上并连接到内部命令/地址总线的第二终端电阻器单元。 第一终端电阻器单元包括连接在第一电压源和数据输入缓冲器的第一输入端之间的第一电阻器，第二终端电阻器单元包括连接在第二电压源和命令的第一输入端之间的第二电阻器 /地址输入缓冲区。

公开(公告)号：US07990171B2

公开(公告)日：2011-08-02

申请号：US12245928

申请日：2008-10-06

Applicant: Hoe ju Chung ,  Jung bae Lee ,  Hoon Lee

Inventor： Hoe ju Chung ,  Jung bae Lee ,  Hoon Lee

IPC: G01R31/26

CPC classification number: H01L22/22 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2225/06503 ,  H01L2225/06513 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01055

Abstract: The present invention provides an apparatus including a stacked plurality of devices and a related method. The apparatus includes a stacked plurality of devices including a master device and at least one secondary device; a plurality of segments, each segment being associated with one of the stacked plurality of devices; and a plurality of N vertical connection paths traversing the stacked plurality of devices. The apparatus further includes a plurality of M vertical signal paths configured from the plurality of N vertical connections paths, wherein M is less than N, and at least one of the plurality of M vertical signal paths is a merged vertical signal path adaptively configured by the master device using at least one segment from each one of at least two of the plurality of N vertical connection paths.

Abstract translation: 本发明提供一种包括堆叠的多个装置和相关方法的装置。 该装置包括堆叠的多个装置，包括主装置和至少一个次装置; 多个段，每个段与堆叠的多个设备中的一个相关联; 以及穿过堆叠的多个装置的多个N个垂直连接路径。 该装置还包括由多个N个垂直连接路径构成的多个M个垂直信号路径，其中M小于N，并且多个M个垂直信号路径中的至少一个是被自动配置的合并垂直信号路径 主设备使用来自多个N个垂直连接路径中的至少两个中的每一个的至少一个段。