公开(公告)号：US07915666B2

公开(公告)日：2011-03-29

申请号：US12124143

申请日：2008-05-20

Applicant: Kan Yasui ,  Tetsuya Ishimaru ,  Digh Hisamoto ,  Yasuhiro Shimamoto

Inventor： Kan Yasui ,  Tetsuya Ishimaru ,  Digh Hisamoto ,  Yasuhiro Shimamoto

IPC: H01L29/792

CPC classification number: H01L29/792 ,  G11C16/0425 ,  G11C16/10 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42344

Abstract: An erase method where a corner portion on which an electric field concentrates locally is provided on the memory gate electrode, and charges in the memory gate electrode are injected into a charge trap film in a gate dielectric with Fowler-Nordheim tunneling operation is used. Since current consumption at the time of erase can be reduced by the Fowler-Nordheim tunneling, a power supply circuit area of a memory module can be reduced. Since write disturb resistance can be improved, a memory array area can be reduced by adopting a simpler memory array configuration. Owing to both the effects, an area of the memory module can be largely reduced, so that manufacturing cost can be reduced. Further, since charge injection centers of write and erase coincide with each other, so that (program and erase) endurance is improved.

Abstract translation: 在存储栅电极上设置有局部集中电场的角部的擦除方法，并且使用Fowler-Nordheim隧道操作将存储栅电极中的电荷注入栅极电介质中的电荷陷阱膜。 由于通过Fowler-Nordheim隧道可以减少擦除时的电流消耗，因此可以减少存储器模块的电源电路区域。 由于可以提高写入干扰电阻，所以可以通过采用更简单的存储器阵列配置来减少存储器阵列区域。 由于这两个效果，可以大大减少存储器模块的面积，从而可以降低制造成本。 此外，由于写入和擦除的电荷注入中心彼此一致，所以（编程和擦除）耐久性得到改善。

公开(公告)号：US07847331B2

公开(公告)日：2010-12-07

申请号：US11030900

申请日：2005-01-10

Applicant: Tetsuya Ishimaru ,  Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura

Inventor： Tetsuya Ishimaru ,  Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura

IPC: H01L29/792

CPC classification number: G11C16/0466 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/792

Abstract: In a situation where a memory cell includes an ONO film, which comprises a silicon nitride film for charge storage and oxide films positioned above and below the silicon nitride film; a memory gate above the ONO film; a select gate, which is adjacent to a lateral surface of the memory gate via the ONO film; a gate insulator positioned below the select gate; a source region; and a drain region, an erase operation is performed by injecting holes generated by BTBT into the silicon nitride film while applying a positive potential to the source region, applying a negative potential to the memory gate, applying a positive potential to the select gate, and flowing a current from the drain region to the source region, thus improving the characteristics of a nonvolatile semiconductor memory device.

Abstract translation: 在存储单元包括ONO膜的情况下，其包括用于电荷存储的氮化硅膜和位于氮化硅膜上方和下方的氧化膜; 在ONO电影上方的记忆门; 选择栅极，其经由ONO膜与存储栅的侧表面相邻; 位于选择门下方的栅极绝缘体; 源区; 和漏极区域，通过将BTBT产生的空穴注入氮化硅膜，同时向源极区域施加正电位，向存储栅极施加负电位，向选择栅极施加正电位，进行擦除操作，以及 使电流从漏极区域流向源极区域，从而改善非易失性半导体存储器件的特性。

公开(公告)号：US07667259B2

公开(公告)日：2010-02-23

申请号：US11452256

申请日：2006-06-14

Applicant: Kan Yasui ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shin-Ichiro Kimura

Inventor： Kan Yasui ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shin-Ichiro Kimura

IPC: H01L21/00

CPC classification number: H01L27/115 ,  G11C16/0425 ,  H01L27/11568 ,  H01L29/42344

Abstract: A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of an optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.

Abstract translation: 提供了一种制造非易失性半导体存储器件的方法，其克服了由于利用侧壁结构同时形成自对准分裂栅型存储单元而产生的最佳栅极高度的差异而引入的注入离子的问题，以及 一个缩放的MOS晶体管。 形成在存储区域中形成侧壁的选择栅电极比逻辑区域中的栅电极高，使得自对准分离栅极存储单元的侧壁栅电极的高度大于 在逻辑区域的栅电极。 栅极电极的高度降低在栅电极形成之前的逻辑区域中进行。

公开(公告)号：US07443731B2

公开(公告)日：2008-10-28

申请号：US11727592

申请日：2007-03-27

Applicant: Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

Inventor： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C16/0425 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459

Abstract: An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

Abstract translation: 提供一种稳定运行半导体非易失性存储器件的操作方案。 当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。 因此，可以验证擦除状态，而不知道任何时变变化。 此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

公开(公告)号：US07442986B2

公开(公告)日：2008-10-28

申请号：US11797839

申请日：2007-05-08

Applicant: Kan Yasui ,  Digh Hisamoto ,  Shinichiro Kimura

Inventor： Kan Yasui ,  Digh Hisamoto ,  Shinichiro Kimura

IPC: H01L29/788

CPC classification number: H01L27/11568 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/4232 ,  H01L29/792

Abstract: In a split gate type nonvolatile memory cell in which a MOS transistor for a nonvolatile memory using a charge storing film and a MOS transistor for selecting it are adjacently formed, the charge storing characteristic is improved and the resistance of the gate electrode is reduced. In order to prevent the thickness reduction at the corner portion of the charge storing film and improve the charge storing characteristic, a taper is formed on the sidewall of the select gate electrode. Also, in order to stably perform a silicide process for reducing the resistance of the self-aligned gate electrode, the sidewall of the select gate electrode is recessed. Alternatively, a discontinuity is formed between the upper portion of the self-aligned gate electrode and the upper portion of the select gate electrode.

Abstract translation: 在其中使用电荷存储膜的非易失性存储器的MOS晶体管和用于选择它的MOS晶体管相邻形成的分离栅极型非易失性存储单元中，电荷存储特性得到改善，栅电极的电阻降低。 为了防止电荷存储薄膜的拐角部分的厚度减小并且提高电荷存储特性，在选择栅电极的侧壁上形成锥形。 此外，为了稳定地进行用于降低自对准栅电极的电阻的硅化物工艺，选择栅电极的侧壁凹陷。 或者，在自对准栅电极的上部和选择栅电极的上部之间形成不连续。

公开(公告)号：US20080258205A1

公开(公告)日：2008-10-23

申请号：US12103697

申请日：2008-04-15

Applicant: Tetsuya ISHIMARU ,  Yasuhiro SHIMAMOTO ,  Kan YASUI

Inventor： Tetsuya ISHIMARU ,  Yasuhiro SHIMAMOTO ,  Kan YASUI

IPC: H01L29/792

CPC classification number: H01L29/792 ,  G11C16/14 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/66833

Abstract: An erase current of a non-volatile semiconductor memory device is decreased. A memory cell of the non-volatile semiconductor memory device comprises a source region and a drain region formed in a semiconductor substrate. Over a portion of the semiconductor substrate between the source region and the drain region, a select gate electrode is formed via a gate dielectric film. On a side wall of the select gate electrode, a memory gate electrode is formed via a bottom silicon oxide film and a charge-trapping silicon oxynitride film. In the memory cell configured as above, erase operation is performed as follows. By applying a positive voltage to the memory gate electrode, holes are injected from the memory gate electrode into the silicon oxynitride film to decrease a threshold voltage in a program state to a certain level. Thereafter, hot holes generated by a band-to-band tunneling phenomenon are injected into the silicon oxynitride film and the erase operation is completed.

Abstract translation: 非易失性半导体存储器件的擦除电流减小。 非易失性半导体存储器件的存储单元包括形成在半导体衬底中的源极区域和漏极区域。 在源极区域和漏极区域之间的半导体衬底的一部分上，通过栅极电介质膜形成选择栅电极。 在选择栅电极的侧壁上，经由底部氧化硅膜和电荷俘获氮氧化硅膜形成存储栅电极。 在如上配置的存储单元中，擦除操作如下进行。 通过向存储栅电极施加正电压，将空穴从存储栅电极注入到氧氮化硅膜中，以将程序状态的阈值电压降低到一定水平。 此后，通过带 - 带隧道现象产生的热孔被注入到氧氮化硅膜中，并且擦除操作完成。

公开(公告)号：US07339827B2

公开(公告)日：2008-03-04

申请号：US11147243

申请日：2005-06-08

Applicant: Kan Yasui ,  Digh Hisamoto ,  Toshihiro Tanaka ,  Takashi Yamaki

Inventor： Kan Yasui ,  Digh Hisamoto ,  Toshihiro Tanaka ,  Takashi Yamaki

IPC: G11C16/06 ,  G11C16/32 ,  G11C5/06 ,  G11C16/08 ,  G11C16/24

CPC classification number: G11C16/3418 ,  G11C16/0466 ,  G11C16/3427 ,  H01L27/115 ,  H01L29/4232 ,  H01L29/792

Abstract: In connection with rise and fall of a word line bias, the present invention adopts a procedure such that a diffusion region voltage Vs on a memory transistor side is changed, and after the voltage Vs passes a certain intermediate value Vsx, a gate voltage Vmg of the memory transistor is changed. Alternatively, there is adopted a procedure such that the gate voltage Vmg of the memory transistor is changed, and after the voltage Vmg passes a certain intermediate value Vmgx, the diffusion layer voltage Vs on the memory transistor side is changed. The values of Vsx and Vmgx are determined from the magnitude of the electric field in a gate insulating film not causing FN tunneling electron injection that causes a change in threshold voltage and the magnitude of a potential barrier against holes not causing BTBT hot hole injection.

Abstract translation: 关于字线偏差的上升和下降，本发明采用使存储晶体管侧的扩散区电压Vs变化的过程，在电压Vs经过一定的中间值Vsx之后，栅极电压Vmg为 存储晶体管被改变。 或者，采用使存储晶体管的栅极电压Vmg改变的过程，并且在电压Vmg经过一定的中间值Vmgx之后，存储晶体管侧的扩散层电压Vs被改变。 Vsx和Vmgx的值由栅极绝缘膜中不引起FN隧穿电子注入的电场的大小确定，导致阈值电压的变化以及针对未引起BTBT热空穴注入的孔的势垒的大小。

公开(公告)号：US20070170495A1

公开(公告)日：2007-07-26

申请号：US11639134

申请日：2006-12-15

Applicant: Toshiyuki Mine ,  Kan Yasui ,  Tetsuya Ishimaru ,  Yasuhiro Shimamoto

Inventor： Toshiyuki Mine ,  Kan Yasui ,  Tetsuya Ishimaru ,  Yasuhiro Shimamoto

IPC: H01L29/792

CPC classification number: H01L29/42344 ,  H01L29/512 ,  H01L29/513 ,  H01L29/792 ,  Y10S438/954

Abstract: Performance of a non-volatile semiconductor storage device which performs electron writing by hot electrons and hole erasure by hot holes is improved. A non-volatile memory cell which performs a writing operation by electrons and an erasure operation by holes has a p-type well region, isolation regions, a source region, and a drain region provided on an Si substrate. A control gate electrode is formed via a gate insulating film between the source region and the drain region. In a left-side side wall of the control gate electrode, a bottom Si oxide film, an electric charge holding film, a top Si oxide film, and a memory gate electrode are formed. The electric charge holding film is formed from an Si nitride film stoichiometrically excessively containing silicon.

Abstract translation: 通过热电子进行电子写入和通过热孔进行空穴擦除的非易失性半导体存储装置的性能得到改善。 通过电子执行写入操作和通过空穴的擦除操作的非易失性存储单元具有设置在Si衬底上的p型阱区域，隔离区域，源极区域和漏极区域。 通过栅极绝缘膜在源极区域和漏极区域之间形成控制栅电极。 在控制栅电极的左侧壁形成有底部的氧化硅膜，电荷保持膜，顶部氧化物膜和存储栅电极。 电荷保持膜由化学计量过度地含有硅的氮化硅膜形成。

公开(公告)号：US20060234454A1

公开(公告)日：2006-10-19

申请号：US11404899

申请日：2006-04-17

Applicant: Kan Yasui ,  Shinichiro Kimura ,  Digh Hisamoto ,  Tetsuya Ishimaru

Inventor： Kan Yasui ,  Shinichiro Kimura ,  Digh Hisamoto ,  Tetsuya Ishimaru

IPC: H01L21/336

CPC classification number: H01L29/792 ,  G11C16/0425 ,  G11C16/0466 ,  H01L27/105 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/66833

Abstract: After forming a first dielectric film on the main surface of a semiconductor substrate, a first conductive film is formed on the first dielectric film, and then, the surface of the first conductive film is planarized by a CMP method. Subsequently, the first conductive film and the first dielectric film are etched, thereby forming a select gate having a first gate electrode and a first gate dielectric film. Subsequently, after forming a second dielectric film on the sidewall of the first gate electrode and the main surface, a second conductive film is formed on the second dielectric film, and the second conductive film is etched, thereby forming a memory gate having a second gate electrode and a second gate dielectric film.

Abstract translation: 在半导体衬底的主表面上形成第一电介质膜之后，在第一电介质膜上形成第一导电膜，然后通过CMP方法将第一导电膜的表面平坦化。 随后，蚀刻第一导电膜和第一电介质膜，从而形成具有第一栅极电极和第一栅极电介质膜的选择栅极。 随后，在第一栅电极和主表面的侧壁上形成第二电介质膜之后，在第二电介质膜上形成第二导电膜，并且蚀刻第二导电膜，从而形成具有第二栅极的存储栅极 电极和第二栅极电介质膜。

公开(公告)号：US20050230736A1

公开(公告)日：2005-10-20

申请号：US11030900

申请日：2005-01-10

Applicant: Tetsuya Ishimaru ,  Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura

Inventor： Tetsuya Ishimaru ,  Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura

IPC: G11C16/02 ,  G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C16/0466 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/792

Abstract: In a situation where a memory cell includes an ONO film, which comprises a silicon nitride film for charge storage and oxide films positioned above and below the silicon nitride film; a memory gate above the ONO film; a select gate, which is adjacent to a lateral surface of the memory gate via the ONO film; a gate insulator positioned below the select gate; a source region; and a drain region, an erase operation is performed by injecting holes generated by BTBT into the silicon nitride film while applying a positive potential to the source region, applying a negative potential to the memory gate, applying a positive potential to the select gate, and flowing a current from the drain region to the source region, thus improving the characteristics of a nonvolatile semiconductor memory device.

Abstract translation: 在存储单元包括ONO膜的情况下，其包括用于电荷存储的氮化硅膜和位于氮化硅膜上方和下方的氧化膜; 在ONO电影上方的记忆门; 选择栅极，其经由ONO膜与存储栅的侧表面相邻; 位于选择门下方的栅极绝缘体; 源区; 和漏极区域，通过将BTBT产生的空穴注入氮化硅膜，同时向源极区域施加正电位，向存储栅极施加负电位，向选择栅极施加正电位，进行擦除操作，以及 使电流从漏极区域流向源极区域，从而改善非易失性半导体存储器件的特性。