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    STACKED MEMORY AND FUSE CHIP
    42.
    发明申请
    STACKED MEMORY AND FUSE CHIP 有权
    堆叠存储器和保险丝芯片

    公开(公告)号：US20090213634A1

    公开(公告)日：2009-08-27

    申请号：US12392547

    申请日：2009-02-25

    申请人： Kayoko SHIBATA

    发明人： Kayoko SHIBATA

    IPC分类号： G11C5/02 ,  G11C29/00 ,  G11C17/16

    CPC分类号： G11C17/14 ,  G11C5/02 ,  G11C29/006 ,  G11C29/028 ,  G11C29/80 ,  H01L2224/16

    摘要： A stacked memory comprises one or more memory core chips and a fuse chip. Each of the memory core chips has a memory cell array including spare memory cells for replacing defective memory cells. The fuse chip has a fuse unit including a plurality of fuse elements whose electrical cut state corresponding to a replacement with the spare memory cells can be set. Also the fuse chip has a redundancy cell control circuit for controlling a redundancy cell operation of the defective memory cells based on state information of the fuse unit.

    摘要翻译： 堆叠存储器包括一个或多个存储器核心芯片和熔丝芯片。 每个存储核心芯片具有包括用于替换有缺陷的存储器单元的备用存储单元的存储单元阵列。 熔丝芯片具有包括多个熔丝元件的保险丝单元，其中可以设置与替换备用存储单元相对应的电切断状态。 熔丝芯片还具有冗余单元控制电路，用于基于保险丝单元的状态信息来控制有缺陷的存储器单元的冗余单元操作。

    Memory module and memory system
    44.
    发明申请
    Memory module and memory system 有权
    内存模块和内存系统

    公开(公告)号：US20070081376A1

    公开(公告)日：2007-04-12

    申请号：US11634405

    申请日：2006-12-06

    申请人： Seiji Funaba ,  Yoji Nishio ,  Kayoko Shibata

    发明人： Seiji Funaba ,  Yoji Nishio ,  Kayoko Shibata

    IPC分类号： G11C5/06

    CPC分类号： G11C5/04 ,  G11C5/063 ,  G11C7/1048 ,  G11C11/4093 ,  G11C2207/105 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19107

    摘要： A memory module has a plurality of DRAMs (115), which share a bus line, on the front surface and the back surface of a board. The bus line is connected through a via hole (113) from a terminal (111) to one end of a strip line (112), and the other end of the strip line is connected to a strip line in the other layer through a via hole (119) provided for looping back the line. A termination resistor (120), provided near a termination voltage terminal (VTT), is connected to the looped-back strip line in the other layer through a via hole. The DRAM terminals are connected to the strip line each through a via hole. This memory module is mounted on a motherboard, on which a memory controller is provided, through a connector. The effective characteristic impedance of the bus line is matched with the characteristic impedance of the line in the motherboard.

    摘要翻译： 存储器模块具有在板的前表面和后表面上共享总线的多个DRAM（115）。 总线通过通孔（113）从端子（111）连接到带状线（112）的一端，并且带状线的另一端通过通孔（113）连接到另一层中的带状线 孔（119）用于使线路循环。 设置在终端电压端子（VTT）附近的终端电阻器（120）通过通孔连接到另一层中的环形带状线。 DRAM端子通过通孔连接到带状线。 该存储器模块通过连接器安装在其上提供存储器控制器的母板上。 母线的有效特性阻抗与母板线路特性阻抗匹配。

    Semiconductor device
    45.
    发明申请
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US20060267212A1

    公开(公告)日：2006-11-30

    申请号：US11418094

    申请日：2006-05-05

    申请人： Kayoko Shibata ,  Hiroaki Ikeda

    发明人： Kayoko Shibata ,  Hiroaki Ikeda

    IPC分类号： H01L23/52

    CPC分类号： G11C11/407 ,  H01L23/5226 ,  H01L23/535 ,  H01L23/544 ,  H01L25/0657 ,  H01L2223/5444 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2224/05599

    摘要： A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of through-lines. The numbers associated with the through-line groups are mutually coprime to each other. When one of the through-lines is selected for the each through-line group, one of the semiconductor chip is designated by a combination of the selected through-lines of the plurality of the through-line groups.

    摘要翻译： 公开了一种包括多个半导体芯片和多个通线组的半导体器件。 每个通线组由唯一数量的通线组成。 与通过线组相关联的数字彼此互为互补。 当对于每条直线组选择其中一根直线时，半导体芯片中的一个通过多条通线组中所选择的直通线的组合来指定。

    Semiconductor memory device and stress testing method thereof
    46.
    发明申请
    Semiconductor memory device and stress testing method thereof 有权
    半导体存储器件及其应力测试方法

    公开(公告)号：US20060195734A1

    公开(公告)日：2006-08-31

    申请号：US11349091

    申请日：2006-02-08

    申请人： Kayoko Shibata ,  Hiroaki Ikeda

    发明人： Kayoko Shibata ,  Hiroaki Ikeda

    IPC分类号： G01R31/28

    CPC分类号： G11C29/12 ,  G01R31/2856 ,  G01R31/31721 ,  G11C29/12005 ,  G11C29/1201 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06565 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2224/05552

    摘要： A semiconductor memory device includes a core chip having at least memory cells formed in the core chip, an interface chip having at least peripheral circuits of the memory cells formed in the interface chip, and an external terminal group. The external terminal group includes at least a core power supply terminal that is connected to an internal circuit of the core chip without being connected to an internal circuit of the interface chip, and an interface power supply terminal that is connected to an internal circuit of the interface chip without being connected to the internal circuit of the core chip. With this arrangement, mutually different operation voltages that are optimum for both chips can be given to these chips.

    摘要翻译： 半导体存储器件包括至少具有形成在芯片芯片中的存储器单元的芯片芯片，至少具有形成在接口芯片中的存储单元的外围电路的接口芯片和外部端子组。 外部端子组至少包括与芯片的内部电路连接而不连接到接口芯片的内部电路的核心电源端子，以及连接到内部电路的内部电路的接口电源端子 接口芯片不连接到核心芯片的内部电路。 利用这种布置，可以给这些芯片提供对两个芯片最佳的相互不同的操作电压。

    Memory module and memory system suitable for high speed operation
    47.
    发明授权
    Memory module and memory system suitable for high speed operation 失效
    内存模块和内存系统适合高速运行

    公开(公告)号：US07016212B2

    公开(公告)日：2006-03-21

    申请号：US10630457

    申请日：2003-07-29

    申请人： Kayoko Shibata ,  Yoji Nishio ,  Seiji Funaba

    发明人： Kayoko Shibata ,  Yoji Nishio ,  Seiji Funaba

    IPC分类号： G11C5/06

    CPC分类号： H05K1/0246 ,  H05K2201/10022 ,  H05K2201/10159

    摘要： A memory module comprises a stab resistor between a pin and one end of a bus. A plurality of memory chips is connected to the bus between both ends thereof. A terminating resistor is connected to the other end of the bus. Stab resistance Rs of the stab resistor and terminating resistance Rterm of the terminating resistor are given by: Rs=(N−1)×Zeffdimm/N, and Rterm=Zeffdimm where N represents the number of the memory modules in a memory system; and Zeffdimm, effective impedance of a memory chip arrangement portion consisting of the bus and the memory chips. In the memory system, the memory modules are connected to a memory controller on a motherboard in a stab connection style. Wiring impedance Zmb of the motherboard is given by: Zmb=(2N−1)×Zeffdimm/N2.

    摘要翻译： 存储器模块包括在引脚和总线的一端之间的尖端电阻器。 多个存储器芯片在其两端之间连接到总线。 终端电阻连接到总线的另一端。 尖端电阻的阻抗Rs和终端电阻的终端电阻Rterm由下式给出：<？in-line-formula description =“In-line Formulas”end =“lead”？> Rs =（N-1）xZeffdimm / N和<？in-line-formula description =“In-line Formulas”end =“tail”？> <？in-line-formula description =“In-line Formulas”end =“lead”？> Rterm = Zeffdimm <？in-line-formula description =“在线公式”end =“tail”？>其中N表示存储器系统中的存储器模块的数量; 和Zeffdimm，由总线和存储器芯片组成的存储芯片布置部分的有效阻抗。 在存储器系统中，存储器模块以连接方式连接到主板上的存储器控​​制器。 主板的接线阻抗Zmb由下式给出：<？in-line-formula description =“In-line formula”end =“lead”？> Zmb =（2N-1）xZeffdimm / N < 。<？in-line-formula description =“In-line Formulas”end =“tail”？>

    Register without restriction of number of mounted memory devices and memory module having the same
    49.
    发明授权
    Register without restriction of number of mounted memory devices and memory module having the same 有权
    在不限制安装的存储器件的数量和具有相同的存储器模块的情况下进行注册

    公开(公告)号：US06707726B2

    公开(公告)日：2004-03-16

    申请号：US10206823

    申请日：2002-07-29

    申请人： Yoji Nishio ,  Seiji Funaba ,  Kayoko Shibata ,  Toshio Sugano ,  Hiroaki Ikeda ,  Takuo Iizuka ,  Masayuki Sorimachi

    发明人： Yoji Nishio ,  Seiji Funaba ,  Kayoko Shibata ,  Toshio Sugano ,  Hiroaki Ikeda ,  Takuo Iizuka ,  Masayuki Sorimachi

    IPC分类号： G11C700

    CPC分类号： G11C7/109 ,  G11C7/1078 ,  G11C7/1087 ,  G11C8/06 ,  G11C2207/107

    摘要： First and second pre-processing flip-flops latch a command/address signal inputted to a register by a clock having a frequency of ½ of an external clock signal and an inverse clock thereof. Thus, the command/address signal is decomprossed to a set of signals which temporarily has two times. For example, one of the set of signals has only data contents of an odd-th command/address signal, and the other has only data contents of an even-th command/address signal. Since the set of signals has twice periods of the command/address signal, first and second post-processing flip-flop can latch signals in accordance with an internal clock signal generated by a delay locked loop circuit in a state in which a set-up time and a hold time are sufficiently assured.

    摘要翻译： 第一和第二预处理触发器通过具有外部时钟信号的1/2的频率的时钟及其反时钟来锁存输入到寄存器的命令/地址信号。 因此，命令/地址信号被分解成一组暂时具有两次的信号。 例如，该组信号之一仅具有奇数命令/地址信号的数据内容，而另一个仅具有偶数个命令/地址信号的数据内容。 由于该组信号具有两个命令/地址信号的周期，所以第一和第二后处理触发器可以根据由延迟锁定环电路产生的内部时钟信号来锁存信号， 时间和保持时间充分确保。

    Stacked type semiconductor memory device and chip selection circuit
    50.
    发明授权
    Stacked type semiconductor memory device and chip selection circuit 失效
    堆叠型半导体存储器件和芯片选择电路

    公开(公告)号：US08709871B2

    公开(公告)日：2014-04-29

    申请号：US13293897

    申请日：2011-11-10

    申请人： Junji Yamada ,  Hiroaki Ikeda ,  Kayoko Shibata ,  Yoshihiko Inoue ,  Hitoshi Miwa ,  Tatsuya Ijima

    发明人： Junji Yamada ,  Hiroaki Ikeda ,  Kayoko Shibata ,  Yoshihiko Inoue ,  Hitoshi Miwa ,  Tatsuya Ijima

    IPC分类号： H01L21/66

    CPC分类号： H01L25/0657 ,  G11C5/02 ,  G11C5/04 ,  G11C2029/4402 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2924/01021 ,  H01L2924/15311

    摘要： A stacked type semiconductor memory device of having a structure in which a plurality of semiconductor chips is stacked and a desired semiconductor chip can be selected by assigning a plurality of chip identification numbers different from each other are individually assigned to the plurality of semiconductor chips comprising: a plurality of operation circuits which is connected in cascade in a stacking order of the plurality of semiconductor chips and outputs the plurality of identification numbers different from each other by performing a predetermined operation; and a plurality of comparison circuits which detects whether or not each the identification number and a chip selection address commonly connected to each the semiconductor chip are equal to each other by comparing them.

    摘要翻译： 通过分配彼此不同的多个芯片标识号，具有堆叠多个半导体芯片的结构和可以选择期望的半导体芯片的堆叠型半导体存储器件被分别分配给多个半导体芯片，包括： 多个操作电路，其以所述多个半导体芯片的堆叠顺序级联连接，并通过执行预定的操作输出所述多个不同的识别号码; 以及多个比较电路，通过比较它们来检测每个半导体芯片共同连接的每个识别号码和芯片选择地址是否相等。