公开(公告)号：US07588982B2

公开(公告)日：2009-09-15

申请号：US11512781

申请日：2006-08-29

Applicant: Gurtej S. Sandhu ,  Kirk D. Prall

Inventor： Gurtej S. Sandhu ,  Kirk D. Prall

IPC: H01L21/336

CPC classification number: H01L27/115 ,  H01L21/28273 ,  H01L27/11521

Abstract: Some embodiments include methods of forming flash memory cells and semiconductor constructions, and some embodiments include semiconductor constructions. Some embodiments may include a method in which a semiconductor substrate is provided to have a plurality of active area locations. Floating gates are formed over the active area locations, with the floating gates having widths that are entirely sub-lithographic. Adjacent floating gates are spaced from one another by gaps. Dielectric material and control gate material are formed over the floating gates and within the gaps. Some embodiments may include a construction in which a pair of adjacent floating gates are over a pair of adjacent active areas, with the floating gates being spaced from one another by a distance which is greater than a distance that the active areas are spaced from one another.

Abstract translation: 一些实施例包括形成快闪存储器单元和半导体结构的方法，并且一些实施例包括半导体结构。 一些实施例可以包括其中提供半导体衬底以具有多个有效区域位置的方法。 浮动栅极形成在有源区位置上，浮栅具有完全亚光刻的宽度。 相邻的浮动门通过间隙彼此间隔开。 电介质材料和控制栅极材料形成在浮动栅极和间隙内。 一些实施例可以包括其中一对相邻浮动栅极在一对相邻有效区域之上的结构，其中浮动栅极彼此间隔一定距离，该距离大于有效区域彼此间隔开的距离 。

公开(公告)号：US20090046508A1

公开(公告)日：2009-02-19

申请号：US11496969

申请日：2006-08-01

Applicant: Chun Chen ,  Kirk D. Prall

Inventor： Chun Chen ,  Kirk D. Prall

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C11/5628 ,  G11C16/0483

Abstract: A method is provided for programming a memory cell of an electrically erasable programmable read only memory. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least three programming states. The method includes generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region. The method further includes injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate. A selected threshold voltage for the memory cell corresponding to a selected one of the programming states is generated by applying a selected constant drain-to-source bias voltage and a selected gate voltage.

Abstract translation: 提供了一种用于对电可擦除可编程只读存储器的存储单元进行编程的方法。 存储单元制造在衬底上，并且包括源极区域，漏极区域，浮动栅极和控制栅极。 存储单元具有可选地配置为至少三个编程状态之一的阈值电压。 该方法包括通过在漏极区域和源极区域之间施加漏极 - 源极偏置电压来在漏极区域和源极区域之间产生漏极电流。 该方法还包括通过向控制栅极施加栅极电压将热电子从漏极电流注入到浮置栅极。 通过施加所选择的恒定的漏极 - 源极偏置电压和所选择的栅极电压来产生对应于所选择的编程状态的存储单元的选定阈值电压。

公开(公告)号：US07417280B2

公开(公告)日：2008-08-26

申请号：US11440646

申请日：2006-05-24

Applicant: Kirk D. Prall ,  Chun Chen

Inventor： Kirk D. Prall ,  Chun Chen

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/115

Abstract: A method for forming a flash memory device having a local interconnect connecting source regions of a plurality of transistors within a sector allows for a highly selective wet etch of a dielectric region overlying the source region. An embodiment of the method comprises the use of an etch-resistant layer covering various features such as any gate oxide remaining over the source region, spacers along sidewalls of the transistor stacks, and a capping layer of the transistor. An in-process semiconductor device resulting from the inventive method is also disclosed.

Abstract translation: 用于形成具有连接在扇区内的多个晶体管的源极区域的局部互连的快闪存储器件的方法允许覆盖源极区域的电介质区域的高度选择性的湿蚀刻。 该方法的一个实施例包括使用覆盖各种特征的耐蚀刻层，例如在源极区域上残留的任何栅极氧化物，沿着晶体管叠层的侧壁的间隔物，以及晶体管的覆盖层。 还公开了由本发明方法得到的过程中半导体器件。

公开(公告)号：US20080121969A1

公开(公告)日：2008-05-29

申请号：US11498523

申请日：2006-08-03

Applicant: Gurtej S. Sandhu ,  Kirk D. Prall

Inventor： Gurtej S. Sandhu ,  Kirk D. Prall

IPC: H01L29/788 ,  H01L21/71 ,  H01L29/68 ,  G11C11/34

CPC classification number: H01L29/7881 ,  B82Y10/00 ,  G11C16/0408 ,  G11C2216/06 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/513

Abstract: A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming a second dielectric layer over the nanodots, where the second dielectric layer encases the nanodots. In addition, an intergate dielectric layer is formed over the second dielectric layer. To form sidewalls of the memory cell, a portion of the intergate dielectric layer and a portion of the second dielectric layer are removed with a dry etch, where the sidewalls include a location where a nanodot has been deposited. A spacing layer is formed over the sidewalls to cover the location where a nanodot has been deposited and the remaining portion of the second dielectric layer and the nanodots can be removed with an isotropic etch selective to the second dielectric layer.

Abstract translation: 一种制造存储单元的方法，包括在第一介电层上形成纳米点，并在纳米点上形成第二介电层，其中第二介电层包裹纳米点。 此外，在第二介电层上形成隔间电介质层。 为了形成存储器单元的侧壁，间隔电介质层的一部分和第二电介质层的一部分用干蚀刻去除，其中侧壁包括已经沉积纳米点的位置。 在侧壁上形成间隔层以覆盖已经沉积纳米点的位置，并且可以用对第二介电层选择性的各向同性蚀刻去除第二介电层和纳米点的剩余部分。

公开(公告)号：US07338856B2

公开(公告)日：2008-03-04

申请号：US10649050

申请日：2003-08-27

Applicant: Chun Chen ,  Kirk D. Prall

Inventor： Chun Chen ,  Kirk D. Prall

IPC: H01L21/336 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L29/42332 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7883

Abstract: The present invention provides a method and apparatus for forming a double-doped polysilicon floating gate in a semiconductor memory element. The method includes forming a first dielectric layer on a semiconductor substrate and forming a floating gate above the first dielectric layer, the floating gate comprised of a first layer doped with a first type of dopant material and a second layer doped with a second type of dopant material that is opposite the first type of dopant material in the first layer. The method further includes forming a second dielectric layer above the floating gate, forming a control gate above the second dielectric layer, and forming a source and a drain in the substrate.

Abstract translation: 本发明提供一种在半导体存储元件中形成双掺杂多晶硅浮动栅极的方法和装置。 该方法包括在半导体衬底上形成第一介电层并在第一介电层上形成浮置栅极，浮置栅极包括掺杂有第一类掺杂剂材料的第一层和掺杂有第二类掺杂剂的第二层 与第一层中的第一种掺杂剂材料相反的材料。 该方法还包括在浮置栅极上形成第二电介质层，在第二电介质层上形成控制栅极，以及在衬底中形成源极和漏极。

公开(公告)号：US07269071B2

公开(公告)日：2007-09-11

申请号：US11345982

申请日：2006-02-02

Applicant: Kirk D. Prall ,  Leonard Forbes

Inventor： Kirk D. Prall ,  Leonard Forbes

IPC: G11C11/34 ,  H01L29/792

CPC classification number: H01L27/11568 ,  G11C11/5692 ,  G11C16/0475 ,  H01L27/115

Abstract: An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the substantially vertical structures. The cells can be programmed to have one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed cell operates at reduced drain source current.

公开(公告)号：US07035145B2

公开(公告)日：2006-04-25

申请号：US10998697

申请日：2004-11-29

Applicant: Chun Chen ,  Kirk D. Prall

Inventor： Chun Chen ,  Kirk D. Prall

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G11C16/0483

Abstract: A method is provided for programming a memory cell of an electrically erasable programmable read only memory. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least three programming states. The method includes generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region. The method further includes injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate. A selected threshold voltage for the memory cell corresponding to a selected one of the programming states is generated by applying a selected constant drain-to-source bias voltage and a selected gate voltage.

公开(公告)号：US06924186B2

公开(公告)日：2005-08-02

申请号：US10814640

申请日：2004-04-01

Applicant: Sukesh Sandhu ,  Kirk D. Prall

Inventor： Sukesh Sandhu ,  Kirk D. Prall

IPC: H01L21/28 ,  H01L21/316 ,  H01L21/336 ,  H01L29/51 ,  H01L21/8283

CPC classification number: H01L21/28202 ,  H01L21/02145 ,  H01L21/02178 ,  H01L21/02271 ,  H01L21/02321 ,  H01L21/02351 ,  H01L21/28273 ,  H01L21/3162 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825

Abstract: A novel technique to quench electrical defects in CVD Al2O3 layers is disclosed. A small amount of silicon dopant to the aluminum oxide film reduces the leakage current as well as the gap interface trap density at the dielectric/silicon interface. The implanted silicon gives a better interface and improves the leakage characteristics of the dielectric.

Abstract translation: 公开了一种用于淬灭CVD Al 2 O 3层中的电缺陷的新技术。 氧化铝膜的少量硅掺杂剂减少了漏电流以及电介质/硅界面处的间隙界面陷阱密度。 注入的硅提供更好的界面并改善电介质的泄漏特性。

公开(公告)号：US06812160B2

公开(公告)日：2004-11-02

申请号：US09976624

申请日：2001-10-12

Applicant: Werner Juengling ,  Kirk D. Prall ,  Ravi Iyer ,  Gurtej S. Sandhu ,  Guy Blalock

Inventor： Werner Juengling ,  Kirk D. Prall ,  Ravi Iyer ,  Gurtej S. Sandhu ,  Guy Blalock

IPC: H01L2131

CPC classification number: H01L21/7682 ,  H01L21/02115 ,  H01L21/02118 ,  H01L21/02167 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  Y10T428/12014 ,  Y10T428/24149 ,  Y10T428/249921 ,  Y10T428/25 ,  Y10T428/259 ,  H01L2924/00

Abstract: Methods of forming insulating materials between conductive elements include forming a material adjacent a conductive electrical component comprising: partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. Other methods include forming a material between a pair of conductive electrical components comprising: forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components. Some embodiments include an insulating material adjacent a conductive electrical component, such material comprising a matrix and at least one void within the matrix.

Abstract translation: 在导电元件之间形成绝缘材料的方法包括形成邻近导电电气部件的材料，该材料包括：部分蒸发物质以形成邻近导电电气部件的基体，所述基体在其内具有至少一个空隙。 其他方法包括在一对导电电气部件之间形成材料，包括：在一个质量块内形成一对导电的电气部件，并由该质量块的一大片分隔; 在所述物体的宽度内形成至少一个支撑构件，所述支撑构件不包括导电互连; 以及使所述质量块的膨胀程度有效地在所述支撑构件和所述一对导电电气部件中的每一个之间形成至少一个空隙。 一些实施例包括邻近导电电气部件的绝缘材料，这种材料包括基质和基质内的至少一个空隙。

公开(公告)号：US06624024B1

公开(公告)日：2003-09-23

申请号：US10232221

申请日：2002-08-29

Applicant: Kirk D. Prall ,  Chun Chen

Inventor： Kirk D. Prall ,  Chun Chen

IPC: H01L218247

CPC classification number: H01L27/11521 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/115

Abstract: A method for forming a flash memory device having a local interconnect connecting source regions of a plurality of transistors within a sector allows for a highly-selective wet etch of a dielectric region overlying the source region. An embodiment of the method comprises the use of an etch-resistant layer covering various features such as any gate oxide remaining over the source region, spacers along sidewalls of the transistor stacks, and a capping layer of the transistor. An in-process semiconductor device resulting from the inventive method is also disclosed.

Abstract translation: 用于形成具有连接在扇区内的多个晶体管的源极区域的局部互连的闪存器件的方法允许覆盖源极区域的电介质区域的高选择性湿蚀刻。 该方法的一个实施例包括使用覆盖各种特征的耐蚀刻层，例如在源极区域上残留的任何栅极氧化物，沿着晶体管叠层的侧壁的间隔物，以及晶体管的覆盖层。 还公开了由本发明方法得到的过程中半导体器件。