公开(公告)号：US07205627B2

公开(公告)日：2007-04-17

申请号：US10906510

申请日：2005-02-23

Applicant: James W. Adkisson ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Richard J. Rassel

Inventor： James W. Adkisson ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Richard J. Rassel

IPC: H01L31/06

CPC classification number: H01L27/14609 ,  H01L27/1463 ,  H01L27/14641 ,  H01L27/14643 ,  H01L31/035281

Abstract: A structure (and method for forming the same) for an image sensor cell. The structure includes (a) a semiconductor substrate; (b) a charge collection well on the substrate, the charge collection well comprising a semiconductor material doped with a first doping polarity; (c) a surface pinning layer on and in direct physical contact with the charge collection well, the surface pinning layer comprising a semiconductor material doped with a second doping polarity opposite to the first doping polarity; and (d) an electrically conducting push electrode being in direct physical contact with the surface pinning layer but not being in direct physical contact with the charge collection well.

Abstract translation: 用于图像传感器单元的结构（及其形成方法）。 该结构包括（a）半导体衬底; （b）在所述衬底上的电荷收集阱，所述电荷收集阱包括掺杂有第一掺杂极性的半导体材料; （c）与电荷收集阱直接物理接触的表面钉扎层，所述表面钉扎层包括掺杂有与第一掺杂极性相反的第二掺杂极性的半导体材料; 和（d）与表面钉扎层直接物理接触但不与电荷收集阱直接物理接触的导电推动电极。

公开(公告)号：US07194706B2

公开(公告)日：2007-03-20

申请号：US10710642

申请日：2004-07-27

Applicant: James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Matthew S. Grady ,  Leendert M. Huisman ,  Mark D. Jaffe ,  Phillip J. Nigh ,  Leah M. P. Pastel ,  Thomas G. Sopchak ,  David E. Sweenor ,  David P. Vallett

Inventor： James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Matthew S. Grady ,  Leendert M. Huisman ,  Mark D. Jaffe ,  Phillip J. Nigh ,  Leah M. P. Pastel ,  Thomas G. Sopchak ,  David E. Sweenor ,  David P. Vallett

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G01R31/31855 ,  G01R31/318586 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is disclosed for designing scan chains in an integrated circuit chip with specific parameter sensitivities to identify fabrication process defects causing test fails and chip yield loss. The composition of scan paths in the integrated circuit chip is biased to allow them to also function as on-product process monitors. The method adds grouping constraints that bias scan chains to have common latch cell usage where possible, and also biases cell routing to constrain scan chain routing to given restricted metal layers for interconnects. The method assembles a list of latch design parameters which are sensitive to process variation or integrity, and formulates a plan for scan chain design which determines the number and the length of scan chains. A model is formulated of scan chain design based upon current state of yield and process integrity, wherein certain latch designs having dominant sensitivities are chosen for specific ones of the scan chains on the chip. The model is provided as input parameters to a global placement and wiring program used to lay out the scan chains. Test data on the chip is then analyzed to determine and isolate systematic yield problems denoted by attributes of a statistically significant failing population of a specific type of scan chain.

Abstract translation: 公开了一种用于设计具有特定参数灵敏度的集成电路芯片中的扫描链的方法，以识别导致测试失败和芯片产量损失的制造工艺缺陷。 集成电路芯片中的扫描路径的组成被偏置以允许它们也用作产品过程监视器。 该方法增加了分组约束，使得扫描链偏置以在可能的情况下具有共同的锁存单元使用，并且还偏置小区路由以将扫描链路由限制到用于互连的给定受限金属层。 该方法组合了对过程变化或完整性敏感的锁存器设计参数列表，并且制定了扫描链设计的计划，该计划确定了扫描链的数量和长度。 基于产量和过程完整性的当前状态来制定扫描链设计的模型，其中为芯片上的特定扫描链选择具有主要灵敏度的某些锁存器设计。 该模型作为输入参数提供给用于布置扫描链的全局放置和布线程序。 然后对芯片上的测试数据进行分析，以确定和分离由特定类型的扫描链的统计学显着失败群体的属性表示的系统产量问题。

公开(公告)号：US5734192A

公开(公告)日：1998-03-31

申请号：US581680

申请日：1995-12-22

Applicant: Edward W. Sengle ,  Mark D. Jaffe ,  Daniel Nelson Maynard ,  Mark Alan Lavin ,  Eric Jeffrey White ,  John A. Bracchitta

Inventor： Edward W. Sengle ,  Mark D. Jaffe ,  Daniel Nelson Maynard ,  Mark Alan Lavin ,  Eric Jeffrey White ,  John A. Bracchitta

IPC: H01L21/762 ,  H01L23/522 ,  H01L29/00

CPC classification number: H01L21/76224 ,  H01L23/5222 ,  H01L2924/0002

Abstract: A trench isolation structure for a semiconductor is provided including an isolation ring and an isolation path. The isolation ring surrounds active semiconductor areas and is bordered on the outside by inactive semiconductor area. The isolation path extends from the isolation ring through the inactive semiconductor area. A first level conductor on the isolation path electrically connects or capacitively couples a device in the active semiconductor area to a location on the substrate outside the isolation ring. The isolation path has a configuration derived from the layout of the conductor.

公开(公告)号：US09543356B2

公开(公告)日：2017-01-10

申请号：US12538194

申请日：2009-08-10

Applicant: Jeffrey P. Gambino ,  Mark D. Jaffe ,  John Ellis-Monaghan ,  Richard Rassel

Inventor： Jeffrey P. Gambino ,  Mark D. Jaffe ,  John Ellis-Monaghan ,  Richard Rassel

IPC: H01L27/148 ,  H01L27/146

CPC classification number: H01L27/14689 ,  H01L27/14609 ,  H01L27/14623 ,  H01L27/1464

Abstract: CMOS image sensor pixel sensor cells, methods for fabricating the pixel sensor cells and design structures for fabricating the pixel sensor cells are designed to allow for back side illumination in global shutter mode by providing light shielding from back side illumination of at least one transistor within the pixel sensor cells. In a first particular generalized embodiment, a light shielding layer is located and formed interposed between a first semiconductor layer that includes a photoactive region and a second semiconductor layer that includes the at least a second transistor, or a floating diffusion, that is shielded by the light blocking layer. In a second generalized embodiment, a thin film transistor and a metal-insulator-metal capacitor are used in place of a floating diffusion, and located shielded in a dielectric isolated metallization stack over a carrier substrate.

Abstract translation: CMOS图像传感器像素传感器单元，用于制造像素传感器单元的方法和用于制造像素传感器单元的设计结构被设计成允许在全局快门模式中进行背面照明，通过提供来自至少一个晶体管的背侧照明的光屏蔽 像素传感器单元。 在第一特定广义实施例中，遮光层位于包括光活性区的第一半导体层和包括至少第二晶体管的第二半导体层之间并形成，或者浮置扩散部被屏蔽 遮光层。 在第二广义实施例中，使用薄膜晶体管和金属 - 绝缘体 - 金属电容器来代替浮动扩散，并且被定位在载体衬底上的介电隔离金属化堆叠中。

公开(公告)号：US08796130B2

公开(公告)日：2014-08-05

申请号：US13352851

申请日：2012-01-18

Applicant: Jeffrey P. Gambino ,  Russell T. Herrin ,  Mark D. Jaffe ,  Laura J. Schutz

Inventor： Jeffrey P. Gambino ,  Russell T. Herrin ,  Mark D. Jaffe ,  Laura J. Schutz

IPC: H01L21/3205

CPC classification number: H01L21/823842 ,  H01L21/28052

Abstract: A method patterns a polysilicon gate over two immediately adjacent, opposite polarity transistor devices. The method patterns a mask over the polysilicon gate. The mask has an opening in a location where the opposite polarity transistor devices abut one another. The method then removes some (a portion) of the polysilicon gate through the opening to form at least a partial recess (or potentially a complete opening) in the polysilicon gate. The recess separates the polysilicon gate into a first polysilicon gate and a second polysilicon gate. After forming the recess, the method dopes the first polysilicon gate using a first polarity dopant and dopes the second polysilicon gate using a second polarity dopant having an opposite polarity of the first polarity dopant.

Abstract translation: 一种在两个紧邻的相反极性的晶体管器件上形成多晶硅栅极的方法。 该方法在多晶硅栅极上形成掩模。 掩模在相反极性晶体管器件彼此邻接的位置处具有开口。 然后，该方法通过开口去除多晶硅栅极的一些（一部分），以在多晶硅栅极中形成至少一个部分凹槽（或潜在的完整开口）。 凹槽将多晶硅栅极分离成第一多晶硅栅极和第二多晶硅栅极。 在形成凹槽之后，该方法使用第一极性掺杂剂掺杂第一多晶硅栅极，并使用具有与第一极性掺杂剂相反极性的第二极性掺杂剂掺杂第二多晶硅栅极。

公开(公告)号：US08741739B2

公开(公告)日：2014-06-03

申请号：US13342697

申请日：2012-01-03

Applicant: Alan B. Botula ,  Mark D. Jaffe ,  Alvin J. Joseph

Inventor： Alan B. Botula ,  Mark D. Jaffe ,  Alvin J. Joseph

IPC: H01L21/30

CPC classification number: H01L29/16 ,  H01L21/76254

Abstract: A semiconductor structure and a method of forming the same. In one embodiment, a method of forming a silicon-on-insulator (SOI) wafer substrate includes: providing a handle substrate; forming a high resistivity material layer over the handle substrate, the high resistivity material layer including one of an amorphous silicon carbide (SiC), a polycrystalline SiC, an amorphous diamond, or a polycrystalline diamond; forming an insulator layer over the high resistivity material layer; and bonding a donor wafer to a top surface of the insulator layer to form the SOI wafer substrate.

Abstract translation: 半导体结构及其形成方法。 在一个实施例中，形成绝缘体上硅（SOI）晶片衬底的方法包括：提供处理衬底; 在所述手柄衬底上形成高电阻率材料层，所述高电阻率材料层包括非晶碳化硅（SiC），多晶SiC，无定形金刚石或多晶金刚石中的一种; 在所述高电阻率材料层上形成绝缘体层; 并将施主晶片接合到绝缘体层的顶表面以形成SOI晶片衬底。

公开(公告)号：US08729664B2

公开(公告)日：2014-05-20

申请号：US13437273

申请日：2012-04-02

Applicant: Jeffrey P. Gambino ,  Mark D. Jaffe ,  Mark D. Levy ,  John C. Malinowski

Inventor： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Mark D. Levy ,  John C. Malinowski

IPC: H01L29/15 ,  H01L23/52 ,  H01L29/47 ,  H01L27/095

CPC classification number: H01L29/0619 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit chip comprising a guard ring formed on a semiconductor substrate that surrounds the active region of the integrated circuit chip and extends from the semiconductor substrate through one or more of a plurality of wiring levels. The guard ring comprises stacked metal lines with spaces breaking up each respective metal line. Each space may be formed such that it partially overlies the space in the metal line directly below but does not overlie any other space. Alternatively, each space may also be formed such that each space is at least completely overlying the space in the metal line below it.

Abstract translation: 一种集成电路芯片，包括形成在半导体衬底上的保护环，所述保护环围绕所述集成电路芯片的有源区并从所述半导体衬底延伸穿过多个布线层中的一个或多个。 保护环包括堆叠金属线，空间分开各个金属线。 每个空间可以被形成为使得其部分地覆盖金属线中的空间直接在下方，但不覆盖任何其它空间。 或者，每个空间也可以形成为使得每个空间至少完全覆盖在其下面的金属线中的空间。

公开(公告)号：US08723392B2

公开(公告)日：2014-05-13

申请号：US13183977

申请日：2011-07-15

Applicant: James W. Adkisson ,  Panglijen Candra ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Anthony K. Stamper ,  Randy L. Wolf

Inventor： James W. Adkisson ,  Panglijen Candra ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Anthony K. Stamper ,  Randy L. Wolf

IPC: H03H9/25

CPC classification number: H03H9/14538 ,  H03H3/08

Abstract: Disclosed herein is a surface acoustic wave (SAW) filter and method of making the same. The SAW filter includes a piezoelectric substrate; a planar barrier layer disposed above the piezoelectric substrate, and at least one conductor buried in the piezoelectric substrate and the planar barrier layer.

Abstract translation: 本文公开了一种表面声波（SAW）滤波器及其制造方法。 SAW滤波器包括压电基片; 设置在所述压电基板上方的平面阻挡层，以及埋设在所述压电基板和所述平面阻挡层中的至少一个导体。

公开(公告)号：US08536035B2

公开(公告)日：2013-09-17

申请号：US13363603

申请日：2012-02-01

Applicant: Alan B. Botula ,  Mark D. Jaffe ,  Alvin J. Joseph ,  Kenneth F. McAvey ,  Gerd Pfeiffer ,  Richard A. Phelps

Inventor： Alan B. Botula ,  Mark D. Jaffe ,  Alvin J. Joseph ,  Kenneth F. McAvey ,  Gerd Pfeiffer ,  Richard A. Phelps

IPC: H01L21/425

CPC classification number: H01L21/76254

Abstract: Silicon-on-insulator (SOI) structures and related methods of forming such structures. In one case, a method includes providing a silicon-on-insulator (SOI) handle substrate having: a substantially uniform resistivity profile along a depth of the handle substrate; and an interstitial oxygen (Oi) concentration of less than approximately 10 parts per million atoms (ppma). The method further includes counter-doping a surface region of the handle, causing the surface region to have a resistivity greater than approximately 3 kOhm-cm, and joining the surface region of the handle substrate with a donor wafer.

Abstract translation: 绝缘体上硅（SOI）结构和形成这种结构的相关方法。 在一种情况下，一种方法包括提供绝缘体上硅（SOI）手柄衬底，其具有：沿着手柄衬底的深度的基本均匀的电阻率分布; 和间隙氧（Oi）浓度小于约10ppm（ppma）。 所述方法还包括对所述手柄的表面区域进行反掺杂，使所述表面区域具有大于约3kOhm-cm的电阻率，并且将所述手柄衬底的表面区域与施主晶片接合。

公开(公告)号：US20130181293A1

公开(公告)日：2013-07-18

申请号：US13352851

申请日：2012-01-18

Applicant: Jeffrey P. Gambino ,  Russell T. Herrin ,  Mark D. Jaffe ,  Laura J. Schutz

Inventor： Jeffrey P. Gambino ,  Russell T. Herrin ,  Mark D. Jaffe ,  Laura J. Schutz

IPC: H01L27/088 ,  H01L21/28

CPC classification number: H01L21/823842 ,  H01L21/28052

Abstract: A method patterns a polysilicon gate over two immediately adjacent, opposite polarity transistor devices. The method patterns a mask over the polysilicon gate. The mask has an opening in a location where the opposite polarity transistor devices abut one another. The method then removes some (a portion) of the polysilicon gate through the opening to form at least a partial recess (or potentially a complete opening) in the polysilicon gate. The recess separates the polysilicon gate into a first polysilicon gate and a second polysilicon gate. After forming the recess, the method dopes the first polysilicon gate using a first polarity dopant and dopes the second polysilicon gate using a second polarity dopant having an opposite polarity of the first polarity dopant.

Abstract translation: 一种在两个紧邻的相反极性的晶体管器件上形成多晶硅栅极的方法。 该方法在多晶硅栅极上形成掩模。 掩模在相反极性晶体管器件彼此邻接的位置处具有开口。 然后，该方法通过开口去除多晶硅栅极的一些（一部分），以在多晶硅栅极中形成至少一个部分凹槽（或潜在的完整开口）。 凹槽将多晶硅栅极分离成第一多晶硅栅极和第二多晶硅栅极。 在形成凹槽之后，该方法使用第一极性掺杂剂掺杂第一多晶硅栅极，并使用具有与第一极性掺杂剂相反极性的第二极性掺杂剂掺杂第二多晶硅栅极。