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118 条记录 (耗时 0.03 秒)

    Discontinuous guard ring
    1.
    发明授权
    Discontinuous guard ring 有权
    不连续的护环

    公开(公告)号：US08729664B2

    公开(公告)日：2014-05-20

    申请号：US13437273

    申请日：2012-04-02

    申请人： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Mark D. Levy ,  John C. Malinowski

    发明人： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Mark D. Levy ,  John C. Malinowski

    IPC分类号： H01L29/15 ,  H01L23/52 ,  H01L29/47 ,  H01L27/095

    CPC分类号： H01L29/0619 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit chip comprising a guard ring formed on a semiconductor substrate that surrounds the active region of the integrated circuit chip and extends from the semiconductor substrate through one or more of a plurality of wiring levels. The guard ring comprises stacked metal lines with spaces breaking up each respective metal line. Each space may be formed such that it partially overlies the space in the metal line directly below but does not overlie any other space. Alternatively, each space may also be formed such that each space is at least completely overlying the space in the metal line below it.

    摘要翻译： 一种集成电路芯片，包括形成在半导体衬底上的保护环，所述保护环围绕所述集成电路芯片的有源区并从所述半导体衬底延伸穿过多个布线层中的一个或多个。 保护环包括堆叠金属线，空间分开各个金属线。 每个空间可以被形成为使得其部分地覆盖金属线中的空间直接在下方，但不覆盖任何其它空间。 或者，每个空间也可以形成为使得每个空间至少完全覆盖在其下面的金属线中的空间。

    DISCONTINUOUS GUARD RING
    2.
    发明申请
    DISCONTINUOUS GUARD RING 有权
    不连续的保护环

    公开(公告)号：US20130256826A1

    公开(公告)日：2013-10-03

    申请号：US13437273

    申请日：2012-04-02

    申请人： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Mark D. Levy ,  John C. Malinowski

    发明人： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Mark D. Levy ,  John C. Malinowski

    IPC分类号： H01L29/06

    CPC分类号： H01L29/0619 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit chip comprising a guard ring formed on a semiconductor substrate that surrounds the active region of the integrated circuit chip and extends from the semiconductor substrate through one or more of a plurality of wiring levels. The guard ring comprises stacked metal lines with spaces breaking up each respective metal line. Each space may be formed such that it partially overlies the space in the metal line directly below but does not overlie any other space. Alternatively, each space may also be formed such that each space is at least completely overlying the space in the metal line below it.

    摘要翻译： 一种集成电路芯片，包括形成在半导体衬底上的保护环，所述保护环围绕所述集成电路芯片的有源区并且从所述半导体衬底延伸通过多个布线层中的一个或多个。 保护环包括堆叠金属线，空间分开各个金属线。 每个空间可以被形成为使得其部分地覆盖金属线中的空间直接在下方，但不覆盖任何其它空间。 或者，每个空间也可以形成为使得每个空间至少完全覆盖在其下面的金属线中的空间。

    CMOS imager with Cu wiring and method of eliminating high reflectivity interfaces therefrom
    5.
    发明授权
    CMOS imager with Cu wiring and method of eliminating high reflectivity interfaces therefrom 失效
    具有Cu布线的CMOS成像器和从其中消除高反射率界面的方法

    公开(公告)号：US07772028B2

    公开(公告)日：2010-08-10

    申请号：US11959841

    申请日：2007-12-19

    申请人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel ,  Anthony K. Stamper

    发明人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel ,  Anthony K. Stamper

    IPC分类号： H01L21/66

    CPC分类号： H01L27/14636 ,  H01L21/76819 ,  H01L21/76834 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14645 ,  H01L27/14683

    摘要： A CMOS image sensor and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack to result in a pixel array exhibiting increased light sensitivity. The CMOS image sensor includes structures having a minimum thickness of barrier layer metal that traverses the optical path of each pixel in the sensor array or, that have portions of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer may be formed atop the Cu metallization by a self-aligned deposition.

    摘要翻译： CMOS图像传感器和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合较薄的层间电介质堆叠以产生呈现增加的光灵敏度的像素阵列。 CMOS图像传感器包括具有穿过传感器阵列中的每个像素的光路的阻挡层金属的最小厚度的结构，或者具有从每个像素的光路中选择性地去除的阻挡层金属的部分，从而使反射率最小化的结构。 也就是说，通过实现各种块或单掩模方法，在阵列中的每个像素的光路的位置处完全去除了阻挡层金属的部分。 在另一个实施例中，阻挡金属层可以通过自对准沉积形成在Cu金属化之上。

    Damascene copper wiring optical image sensor
    6.
    发明授权
    Damascene copper wiring optical image sensor 有权
    大马士革铜线接线光学图像传感器

    公开(公告)号：US07655495B2

    公开(公告)日：2010-02-02

    申请号：US11623977

    申请日：2007-01-17

    申请人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Anthony K. Stamper

    发明人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Anthony K. Stamper

    IPC分类号： H01L21/00

    CPC分类号： H01L27/14685 ,  H01L21/76819 ,  H01L21/76834 ,  H01L21/76838 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14687

    摘要： A CMOS image sensor array and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack with improved thickness uniformity to result in a pixel array exhibiting increased light sensitivity. In the sensor array, each Cu metallization level includes a Cu metal wire structure formed at locations between each array pixel and, a barrier material layer is formed on top each Cu metal wire structure that traverses the pixel optical path. By implementing a single mask or self-aligned mask methodology, a single etch is conducted to completely remove the interlevel dielectric and barrier layers that traverse the optical path. The etched opening is then refilled with dielectric material. Prior to depositing the refill dielectric, a layer of either reflective or absorptive material is formed along the sidewalls of the etched opening to improve sensitivity of the pixels by either reflecting light to the underlying photodiode or by eliminating light reflections.

    摘要翻译： CMOS图像传感器阵列和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合更薄的层间电介质叠层，具有改进的厚度均匀性，以产生呈现增加的光敏度的像素阵列。 在传感器阵列中，每个Cu金属化层包括在每个阵列像素之间的位置处形成的Cu金属线结构，并且阻挡材料层形成在穿过像素光路的每个Cu金属线结构上。 通过实现单掩模或自对准掩模方法，进行单次蚀刻以完全去除穿过光路的层间电介质层和阻挡层。 然后将蚀刻的开口用电介质材料重新填充。 在沉积再充填电介质之前，沿蚀刻开口的侧壁形成反射或吸收材料层，以通过将光反射到下面的光电二极管或通过消除光反射来提高像素的灵敏度。

    THREE DIMENSIONAL VERTICAL E-FUSE STRUCTURES AND METHODS OF MANUFACTURING THE SAME
    8.
    发明申请
    THREE DIMENSIONAL VERTICAL E-FUSE STRUCTURES AND METHODS OF MANUFACTURING THE SAME 失效
    三维垂直电子熔断器结构及其制造方法

    公开(公告)号：US20090085152A1

    公开(公告)日：2009-04-02

    申请号：US11865079

    申请日：2007-10-01

    申请人： Kerry Bernstein ,  Timothy J. Dalton ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Stephen E. Luce ,  Anthony K. Stamper

    发明人： Kerry Bernstein ,  Timothy J. Dalton ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Stephen E. Luce ,  Anthony K. Stamper

    IPC分类号： H01L23/62 ,  H01L21/44

    CPC分类号： H01L23/5256 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Three dimensional vertical e-fuse structures and methods of manufacturing the same are provided herein. The method of forming a fuse structure comprises providing a substrate including an insulator layer and forming an opening in the insulator layer. The method further comprises forming a conductive layer along a sidewall of the opening and filling the opening with an insulator material. The vertical e-fuse structure comprises a first contact layer and a second contact layer. The structure further includes a conductive material lined within a via and in electrical contact with the first contact layer and the second contact layer. The conductive material has an increased resistance as a current is applied thereto.

    摘要翻译： 本文提供三维垂直电子熔丝结构及其制造方法。 形成熔丝结构的方法包括提供包括绝缘体层并在绝缘体层中形成开口的衬底。 该方法还包括沿着开口的侧壁形成导电层并用绝缘体材料填充开口。 垂直e熔丝结构包括第一接触层和第二接触层。 该结构还包括衬里在通孔内并与第一接触层和第二接触层电接触的导电材料。 当施加电流时，导电材料具有增加的电阻。