公开(公告)号：US09040378B2

公开(公告)日：2015-05-26

申请号：US14309018

申请日：2014-06-19

Applicant: Bo-Young Lee ,  Jong-Wan Choi ,  Dae-Hun Choi ,  Myoung-Bum Lee

Inventor： Bo-Young Lee ,  Jong-Wan Choi ,  Dae-Hun Choi ,  Myoung-Bum Lee

IPC: H01L21/336 ,  H01L27/115 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L27/11556 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/7827

Abstract: Methods of forming semiconductor devices including vertical channels and semiconductor devices formed using such methods are provided. The methods may include forming a stack including a plurality of insulating patterns alternating with a plurality of conductive patterns on an upper surface of a substrate and forming a hole through the stack. The hole may expose sidewalls of the plurality of insulating patterns and the plurality of conductive patterns. The sidewalls of the plurality of insulating patterns may be aligned along a first plane that is slanted with respect to the upper surface of the substrate, and midpoints of the respective sidewalls of the plurality of conductive patterns may be aligned along a second plane that is substantially perpendicular to the upper surface of the substrate.

Abstract translation: 提供了使用这种方法形成的包括垂直沟道和半导体器件的半导体器件的形成方法。 所述方法可以包括形成堆叠，其包括与衬底的上表面上的多个导电图案交替的多个绝缘图案，并且通过堆叠形成孔。 孔可以暴露多个绝缘图案和多个导电图案的侧壁。 多个绝缘图案的侧壁可以沿着相对于衬底的上表面倾斜的第一平面对齐，并且多个导电图案的相应侧壁的中点可以沿着基本上 垂直于衬底的上表面。

公开(公告)号：US08536652B2

公开(公告)日：2013-09-17

申请号：US13224427

申请日：2011-09-02

Applicant: Bo-young Lee ,  Jong-wan Choi ,  Jin-gi Hong ,  Myoung-bum Lee

Inventor： Bo-young Lee ,  Jong-wan Choi ,  Jin-gi Hong ,  Myoung-bum Lee

IPC: H01L29/78

CPC classification number: H01L21/764 ,  H01L27/11521 ,  H01L27/11568

Abstract: A method of manufacturing a non-volatile memory device, can be provided by forming a gate insulating layer and a gate conductive layer on a substrate that includes active regions that are defined by device isolation regions that include a carbon-containing silicon oxide layer. The gate conductive layer and the gate insulating layer can be sequentially etched to expose the carbon-containing silicon oxide layer. The carbon-containing silicon oxide layer can be wet-etched to recess a surface of the carbon-containing silicon oxide layer to below a surface of the substrate. Then, an interlayer insulating layer can be formed between the gate insulating layer and the gate conductive layer on the carbon-containing silicon oxide layer, where an air gap can be formed between the carbon-containing silicon oxide layer and the gate insulating layer.

Abstract translation: 可以通过在包括由包含含碳氧化硅层的器件隔离区限定的有源区的衬底上形成栅极绝缘层和栅极导电层来提供制造非易失性存储器件的方法。 可以依次蚀刻栅极导电层和栅极绝缘层，以露出含碳氧化硅层。 可以对含碳氧化硅层进行湿蚀刻，以将含碳氧化硅层的表面凹入到衬底的表面下方。 然后，可以在含碳氧化硅层上的栅极绝缘层和栅极导电层之间形成层间绝缘层，其中可以在含碳氧化硅层和栅极绝缘层之间形成气隙。

公开(公告)号：US07646067B2

公开(公告)日：2010-01-12

申请号：US11891337

申请日：2007-08-10

Applicant: Gab-Jin Nam ,  Myoung-Bum Lee

Inventor： Gab-Jin Nam ,  Myoung-Bum Lee

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/01 ,  H01L27/12 ,  H01L23/62

CPC classification number: H01L21/823842 ,  Y10S257/914

Abstract: A CMOS transistor and a method of manufacturing the CMOS transistor are disclosed. An NMOS transistor is formed on a first region of a semiconductor substrate. A PMOS transistor is formed on a second region of a semiconductor substrate. The NMOS transistor includes a first gate conductive layer. The PMOS transistor includes a second gate conductive layer. The first gate conductive layer includes a metal having a nitrogen concentration increasing in a direction from a lower portion toward an upper portion. In addition, the metal has a work function of about 4.0 eV to about 4.3 eV. The third gate conductive layer includes a metal having a nitrogen concentration increasing in a direction from a lower portion toward an upper portion. In addition, the metal has a work function of about 4.7 eV to about 5.0 eV.

Abstract translation: 公开了CMOS晶体管和制造CMOS晶体管的方法。 NMOS晶体管形成在半导体衬底的第一区域上。 PMOS晶体管形成在半导体衬底的第二区域上。 NMOS晶体管包括第一栅极导电层。 PMOS晶体管包括第二栅极导电层。 第一栅极导电层包括在从下部朝向上部的方向上氮浓度增加的金属。 此外，金属具有约4.0eV至约4.3eV的功函数。 第三栅极导电层包括在从下部朝向上部的方向上氮浓度增加的金属。 此外，金属具有约4.7eV至约5.0eV的功函数。

公开(公告)号：US20080042213A1

公开(公告)日：2008-02-21

申请号：US11891337

申请日：2007-08-10

Applicant: Gab-Jin Nam ,  Myoung-Bum Lee

Inventor： Gab-Jin Nam ,  Myoung-Bum Lee

IPC: H01L21/8238 ,  H01L29/94

CPC classification number: H01L21/823842 ,  Y10S257/914

Abstract: A CMOS transistor and a method of manufacturing the CMOS transistor are disclosed. An NMOS transistor is formed on a first region of a semiconductor substrate. A PMOS transistor is formed on a second region of a semiconductor substrate. The NMOS transistor includes a first gate conductive layer. The PMOS transistor includes a second gate conductive layer. The first gate conductive layer includes a metal having a nitrogen concentration increasing in a direction from a lower portion toward an upper portion. In addition, the metal has a work function of about 4.0 eV to about 4.3 eV. The third gate conductive layer includes a metal having a nitrogen concentration increasing in a direction from a lower portion toward an upper portion. In addition, the metal has a work function of about 4.7 eV to about 5.0 eV.

Abstract translation: 公开了CMOS晶体管和制造CMOS晶体管的方法。 NMOS晶体管形成在半导体衬底的第一区域上。 PMOS晶体管形成在半导体衬底的第二区域上。 NMOS晶体管包括第一栅极导电层。 PMOS晶体管包括第二栅极导电层。 第一栅极导电层包括在从下部朝向上部的方向上氮浓度增加的金属。 此外，金属具有约4.0eV至约4.3eV的功函数。 第三栅极导电层包括在从下部朝向上部的方向上氮浓度增加的金属。 此外，金属具有约4.7eV至约5.0eV的功函数。

公开(公告)号：US07211769B2

公开(公告)日：2007-05-01

申请号：US10115111

申请日：2002-04-01

Applicant: Byung-Hee Kim ,  Jong-Myeong Lee ,  Myoung-Bum Lee ,  Ju-Young Yun ,  Gil-Heyun Choi

Inventor： Byung-Hee Kim ,  Jong-Myeong Lee ,  Myoung-Bum Lee ,  Ju-Young Yun ,  Gil-Heyun Choi

IPC: F27B5/14

CPC classification number: H01L21/67109 ,  C30B25/10 ,  C30B31/14

Abstract: A heating chamber which can be used during a reflow process to form a metal wiring having a multi-layered writing structure and a method of heating a wafer using the same, are provided. The heating chamber is movable upward and downward between the upper process position and the lower loading position, and includes a pedestal having a supporting surface for supporting a wafer, a cover installed above the pedestal to form a processing area together with the supporting surface when the pedestal is placed in its raised process position and a heating unit for heating the waver. In the method of heating the wafer, the temperature in the processing area is maintained suitable for heating the wafer before the wafer is loaded onto the supporting surface, the wafer is loaded onto the supporting surface and the loaded wafer is heating in the processing area.

Abstract translation: 提供了可以在回流工艺期间使用以形成具有多层书写结构的金属布线的加热室和使用其加热晶片的方法。 加热室可以在上部处理位置和下部装载位置之间上下移动，并且包括具有用于支撑晶片的支撑表面的基座，安装在基座上方的盖子，当与该支撑表面一起形成处理区域时 基座放置在其升高的处理位置和用于加热摇摆的加热单元。 在加热晶片的方法中，在将晶片加载到支撑表面之前，处理区域中的温度保持适于加热晶片，晶片被加载到支撑表面上，并且加载的晶片在处理区域中被加热。

公开(公告)号：US06399457B2

公开(公告)日：2002-06-04

申请号：US09862733

申请日：2001-05-21

Applicant: Byung-lyul Park ,  Myoung-bum Lee ,  Hyeon-deok Lee

Inventor： Byung-lyul Park ,  Myoung-bum Lee ,  Hyeon-deok Lee

IPC: H01L2120

CPC classification number: H01L28/60 ,  H01L21/31604 ,  H01L27/1085 ,  Y10S438/915 ,  Y10S438/919

Abstract: A semiconductor device having a capacitor. The capacitor includes a first electrode, a dielectric layer formed of a metal oxide layer including a Ta2O5 layer, and a second electrode composed of first and second metal nitride layers sequentially stacked. Each of the first and second metal nitride layers has a TiN layer and a WN layer. The second electrode of the capacitor is a double-layered structure having the first and second metal nitride layers, and thus annealing after forming the second electrode is performed at 750° C. or less, to thereby reduce an equivalent oxide thickness of the dielectric layer.

Abstract translation: 一种具有电容器的半导体器件。 电容器包括第一电极，由包括Ta 2 O 5层的金属氧化物层形成的电介质层和由顺序堆叠的第一和第二金属氮化物层构成的第二电极。 第一和第二金属氮化物层中的每一个具有TiN层和WN层。 电容器的第二电极是具有第一和第二金属氮化物层的双层结构，因此在750℃或更低的温度下进行形成第二电极之后的退火，从而降低电介质层的等效氧化物厚度 。

公开(公告)号：US06261890B1

公开(公告)日：2001-07-17

申请号：US09209651

申请日：1998-12-10

Applicant: Byung-lyul Park ,  Myoung-bum Lee ,  Hyeon-deok Lee

Inventor： Byung-lyul Park ,  Myoung-bum Lee ,  Hyeon-deok Lee

IPC: H01L218234

CPC classification number: H01L28/60 ,  H01L21/31604 ,  H01L27/1085 ,  Y10S438/915 ,  Y10S438/919

Abstract: The capacitor of semiconductor devices includes a first electrode, a dielectric layer formed of a metal oxide layer including a Ta2O5 layer, and a second electrode composed of first and second metal nitride layers sequentially stacked. First and second metal nitride layers are a TiN layer and a WN layer. The second electrode of the capacitor is a double-layered structure having the first and second metal nitride layers, and thus annealing after forming the second electrode is performed at 750° C. or less to avoid increasing an equivalent oxide thickness of the dielectric layer.

Abstract translation: 半导体器件的电容器包括第一电极，由包括Ta 2 O 5层的金属氧化物层形成的电介质层和由顺序层叠的第一和第二金属氮化物层构成的第二电极。 第一和第二金属氮化物层是TiN层和WN层。 电容器的第二电极是具有第一和第二金属氮化物层的双层结构，因此在形成第二电极之后的退火在750℃以下进行，以避免增加电介质层的等效氧化物厚度。