公开(公告)号：US07211769B2

公开(公告)日：2007-05-01

申请号：US10115111

申请日：2002-04-01

申请人： Byung-Hee Kim ,  Jong-Myeong Lee ,  Myoung-Bum Lee ,  Ju-Young Yun ,  Gil-Heyun Choi

发明人： Byung-Hee Kim ,  Jong-Myeong Lee ,  Myoung-Bum Lee ,  Ju-Young Yun ,  Gil-Heyun Choi

IPC分类号： F27B5/14

CPC分类号： H01L21/67109 ,  C30B25/10 ,  C30B31/14

摘要： A heating chamber which can be used during a reflow process to form a metal wiring having a multi-layered writing structure and a method of heating a wafer using the same, are provided. The heating chamber is movable upward and downward between the upper process position and the lower loading position, and includes a pedestal having a supporting surface for supporting a wafer, a cover installed above the pedestal to form a processing area together with the supporting surface when the pedestal is placed in its raised process position and a heating unit for heating the waver. In the method of heating the wafer, the temperature in the processing area is maintained suitable for heating the wafer before the wafer is loaded onto the supporting surface, the wafer is loaded onto the supporting surface and the loaded wafer is heating in the processing area.

摘要翻译： 提供了可以在回流工艺期间使用以形成具有多层书写结构的金属布线的加热室和使用其加热晶片的方法。 加热室可以在上部处理位置和下部装载位置之间上下移动，并且包括具有用于支撑晶片的支撑表面的基座，安装在基座上方的盖子，当与该支撑表面一起形成处理区域时 基座放置在其升高的处理位置和用于加热摇摆的加热单元。 在加热晶片的方法中，在将晶片加载到支撑表面之前，处理区域中的温度保持适于加热晶片，晶片被加载到支撑表面上，并且加载的晶片在处理区域中被加热。

公开(公告)号：US06787468B2

公开(公告)日：2004-09-07

申请号：US10035257

申请日：2002-01-04

申请人： Byung-Hee Kim ,  Jong-Myeong Lee ,  Myoung-Bum Lee ,  Gil-Heyun Choi

发明人： Byung-Hee Kim ,  Jong-Myeong Lee ,  Myoung-Bum Lee ,  Gil-Heyun Choi

IPC分类号： H01L2144

CPC分类号： H01L21/76844 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76882 ,  H01L2221/1089

摘要： A method of fabricating a semiconductor device having a recess region in an insulation layer on a silicon substrate, comprising the steps of depositing a barrier metal over the entire surface of the insulation layer including the substrate surface in the recess region, depositing selectively an anti-nucleation layer on the barrier metal except in the recess region, depositing a CVD-Al layer on the barrier metal in the recess region, depositing a metal or a metal alloy inhibiting aluminum migration on the anti-nucleation layer and the barrier metal except in the recess region, and depositing a PVD-Al layer and re-flowing the PVD-Al layer, for improving the quality of aluminum grooves. The present method inhibits PVD-Al migration and grain growth, which results in preventing abnormal patterning in the semiconductor device.

摘要翻译： 一种制造在硅衬底上的绝缘层中具有凹陷区域的半导体器件的方法，包括以下步骤：在包括凹陷区域中的衬底表面的绝缘层的整个表面上沉积阻挡金属， 在凹陷区域之外的阻挡金属上的成核层，在凹陷区域中的阻挡金属上沉积CVD-Al层，在抗成核层和除了在...中形成的阻挡金属之外沉积抑制铝迁移的金属或金属合金 并且沉积PVD-Al层并再次流动PVD-Al层，以改善铝槽的质量。 本方法抑制PVD-Al迁移和晶粒生长，这导致防止半导体器件中的异常图案化。

公开(公告)号：US06699790B2

公开(公告)日：2004-03-02

申请号：US10035807

申请日：2002-01-04

申请人： Byung-Hee Kim ,  Jong-Myeong Lee ,  Myoung-Bum Lee ,  Gil-Heyun Choi

发明人： Byung-Hee Kim ,  Jong-Myeong Lee ,  Myoung-Bum Lee ,  Gil-Heyun Choi

IPC分类号： H01L21443

CPC分类号： H01L21/76876 ,  H01L21/76843 ,  H01L21/76879 ,  H01L21/76882

摘要： A semiconductor device fabrication method having a recess region in an insulation layer on a silicon substrate, includes the steps of depositing a barrier metal on an entire surface of the insulation layer, filling the recess region with an oxide layer, removing the barrier metal on an upper side of the insulation layer, removing the oxide layer in the recess region and exposing the barrier metal of the recess region, depositing a CVD-Al layer on the barrier metal, and depositing a PVD-Al layer on the CVD-Al layer and re-flowing the PVD-Al layer. The fabrication method of a semiconductor integrated circuit according to the present invention selectively removes a barrier metal in the outside of the recess region to expose the insulation layer to the air, and deposits the CVD-Al layer and the PVD-Al layer, which results in controlling abnormal growth of the CVD-Al metal.

摘要翻译： 一种在硅衬底上的绝缘层中具有凹陷区域的半导体器件制造方法，包括以下步骤：在绝缘层的整个表面上沉积阻挡金属，用氧化物层填充该凹陷区域， 去除所述凹陷区域中的氧化物层并暴露所述凹陷区域的阻挡金属，在所述阻挡金属上沉积CVD-Al层，以及在所述CVD-Al层上沉积PVD-Al层，以及 重新流动PVD-Al层。 根据本发明的半导体集成电路的制造方法选择性地去除凹陷区域的外部的阻挡金属以将绝缘层暴露于空气，并沉积CVD-Al层和PVD-Al层，这导致 控制CVD-Al金属的异常生长。

公开(公告)号：US08404579B2

公开(公告)日：2013-03-26

申请号：US12960150

申请日：2010-12-03

申请人： Sang-Hoon Ahn ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Sang-Don Nam ,  Kyu-Hee Han

发明人： Sang-Hoon Ahn ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Sang-Don Nam ,  Kyu-Hee Han

IPC分类号： H01L21/44

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse base insulating region, for example, an insulating interlayer or a compensation region disposed in an insulating interlayer, is formed on a substrate. An etch stop layer is formed on the fuse base insulating region and forming an insulating interlayer having a lower dielectric constant than the first fuse base insulating region on the etch stop layer. A trench extending through the insulating interlayer and the etch stop layer and at least partially into the fuse base insulating region is formed. A fuse is formed in the trench. The fuse base insulating region may have a greater mechanical strength and/or density than the second insulating interlayer.

摘要翻译： 在衬底上形成熔丝基底绝缘区域，例如绝缘中间层或设置在绝缘中间层中的补偿区域。 在熔丝基底绝缘区上形成蚀刻停止层，形成绝缘中间层，该绝缘中间层的介电常数比蚀刻停止层上的第一熔丝基底绝缘区低。 形成了延伸穿过绝缘中间层和蚀刻停止层并且至少部分地进入熔丝基底绝缘区域的沟槽。 在沟槽中形成熔丝。 保险丝座绝缘区域可具有比第二绝缘中间层更大的机械强度和/或密度。

公开(公告)号：US08304343B2

公开(公告)日：2012-11-06

申请号：US13240109

申请日：2011-09-22

申请人： Kyung-In Choi ,  Hyeon-Deok Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee

发明人： Kyung-In Choi ,  Hyeon-Deok Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee

IPC分类号： H01L21/768

CPC分类号： H01L21/76814 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/76856 ,  H01L27/11526 ,  H01L27/11543 ,  H01L27/11546 ,  H01L27/11548

摘要： In a method of manufacturing a metal wiring structure, a first metal wiring and a first barrier layer are formed on a substrate, and the first barrier layer is nitridated. An insulating interlayer is formed on the substrate so as to extend over the first metal wiring and the first barrier layer. Part of the insulating interlayer is removed to form a hole exposing at least part of the first metal wiring and part of the first barrier layer. A nitridation plasma treatment is performed on the exposed portion of the first barrier layer. A second barrier layer is formed along the bottom and sides of the hole. A plug is formed on the second barrier layer to fill the hole.

摘要翻译： 在制造金属布线结构的方法中，在基板上形成第一金属布线和第一阻挡层，并且对第一阻挡层进行氮化。 绝缘中间层形成在基板上，以便延伸越过第一金属布线和第一阻挡层。 去除部分绝缘中间层以形成露出第一金属布线和第一阻挡层的一部分的至少一部分的孔。 在第一阻挡层的暴露部分上进行氮化等离子体处理。 沿着孔的底部和侧面形成第二阻挡层。 在第二阻挡层上形成插塞以填充孔。

公开(公告)号：US08278207B2

公开(公告)日：2012-10-02

申请号：US12688557

申请日：2010-01-15

申请人： Jin-Ho Park ,  Gil-Heyun Choi ,  Byung-Lyul Park ,  Jong-Myeong Lee ,  Zung-Sun Choi ,  Hye-Kyung Jung

发明人： Jin-Ho Park ,  Gil-Heyun Choi ,  Byung-Lyul Park ,  Jong-Myeong Lee ,  Zung-Sun Choi ,  Hye-Kyung Jung

IPC分类号： H01L21/4763

CPC分类号： H01L21/76846 ,  H01L21/28562 ,  H01L21/76856 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L27/10855 ,  H01L27/11521 ,  H01L27/11524 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device can include an insulation layer on that is on a substrate on which a plurality of lower conductive structures are formed, where the insulation layer has an opening. A barrier layer is on a sidewall and a bottom of the opening of the insulation layer, where the barrier layer includes a first barrier layer in which a constituent of a first deoxidizing material is richer than a metal material in the first barrier layer and a second barrier layer in which a metal material in the second barrier layer is richer than a constituent of a second deoxidizing material. An interconnection is in the opening of which the sidewall and the bottom are covered with the barrier layer, the interconnection is electrically connected to the lower conductive structure.

摘要翻译： 半导体器件可以包括在其上形成有多个下导电结构的基板上的绝缘层，其中绝缘层具有开口。 阻挡层位于绝缘层的开口的侧壁和底部上，其中阻挡层包括第一阻挡层，第一脱氧材料的成分比第一阻挡层中的金属材料更富，第二阻隔层 阻挡层，其中第二阻挡层中的金属材料比第二脱氧材料的成分更富。 互连在其开口中，侧壁和底部被阻挡层覆盖，互连电连接到下导电结构。

公开(公告)号：US20080054468A1

公开(公告)日：2008-03-06

申请号：US11892089

申请日：2007-08-20

申请人： Kyung-In Choi ,  Gil-Heyun Choi ,  Sang-Woo Lee ,  Jong-Myeong Lee ,  Jong-Won Hong ,  Hyun-Bae Lee

发明人： Kyung-In Choi ,  Gil-Heyun Choi ,  Sang-Woo Lee ,  Jong-Myeong Lee ,  Jong-Won Hong ,  Hyun-Bae Lee

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/76868 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： An example embodiment provides a method of forming a conductive pattern in a semiconductor device. The method includes forming one or more dielectric layers over a first conductive pattern formed on a substrate; forming an opening in the one or more dielectric layers to expose a portion of the first conductive pattern, forming a growth promoting layer over the exposed portion of the first conductive pattern and the one or more dielectric layers, forming a growth inhibiting layer over a portion of the growth promoting layer, and forming the second conductive layer in the opening.

摘要翻译： 示例性实施例提供了在半导体器件中形成导电图案的方法。 该方法包括在形成在衬底上的第一导电图案上形成一个或多个电介质层; 在所述一个或多个电介质层中形成开口以暴露所述第一导电图案的一部分，在所述第一导电图案和所述一个或多个介电层的暴露部分上形成增长促进层，在所述第一导电图案的一部分上形成生长抑制层 的生长促进层，并且在开口中形成第二导电层。

公开(公告)号：US20070134932A1

公开(公告)日：2007-06-14

申请号：US11675158

申请日：2007-02-15

申请人： Jung-Hun Seo ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Hee-Sook Park

发明人： Jung-Hun Seo ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Hee-Sook Park

IPC分类号： C23C16/00 ,  H01L21/31

CPC分类号： C23C16/4408 ,  C23C16/54 ,  H01L21/76838 ,  H01L21/76841 ,  H01L21/76861

摘要： A metal deposition processing apparatus includes a first processing chamber configured for holding a semiconductor substrate therein. A second processing chamber is configured for holding the semiconductor substrate therein and for forming an upper metal layer thereon. A transfer chamber is connected to the first processing chamber and the second processing chamber. The transfer chamber is configured to transfer the semiconductor substrate between the first processing chamber and the second processing chamber.

摘要翻译： 金属沉积处理装置包括：第一处理室，被构造成用于将半导体基板保持在其中。 第二处理室构造成用于将半导体衬底保持在其中并用于在其上形成上金属层。 传送室连接到第一处理室和第二处理室。 传送室配置成在第一处理室和第二处理室之间传送半导体衬底。

公开(公告)号：US20050059240A1

公开(公告)日：2005-03-17

申请号：US10857253

申请日：2004-05-28

申请人： Kyung-In Choi ,  Sang-Bom Kang ,  Seong-Geon Park ,  You-Kyoung Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Sang-Woo Lee

发明人： Kyung-In Choi ,  Sang-Bom Kang ,  Seong-Geon Park ,  You-Kyoung Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Sang-Woo Lee

IPC分类号： H01L21/00 ,  H01L21/44 ,  H01L21/84

CPC分类号： H01L21/28556 ,  C23C16/34 ,  C23C16/45553 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76858 ,  H01L21/76862 ,  H01L21/76867 ,  H01L21/76877

摘要： In a method for forming a wiring of a semiconductor device using an atomic layer deposition, an insulating interlayer is formed on a substrate. Tantalum amine derivatives represented by a chemical formula Ta(NR1)(NR2R3)3 in which R1, R2 and R3 represent H or C1-C6 alkyl group are introduced onto the insulating interlayer. A portion of the tantalum amine derivatives is chemisorbed on the insulating interlayer. The rest of tantalum amine derivatives non-chemisorbed on the insulating interlayer is removed from the insulating interlayer. A reacting gas is introduced onto the insulating interlayer. A ligand in the tantalum amine derivatives chemisorbed on the insulating interlayer is removed from the tantalum amine derivatives by a chemical reaction between the reacting gas and the ligand to form a solid material including tantalum nitride. The solid material is accumulated on the insulating interlayer through repeating the above processes to form a wiring.

摘要翻译： 在使用原子层沉积形成半导体器件的布线的方法中，在基板上形成绝缘中间层。 由化学式Ta（NR1）（NR2R3）3表示的钽胺衍生物，其中R 1，R 2和R 3表示H或C 1 -C 6烷基被引入到绝缘中间层上。 一部分钽胺衍生物被化学吸附在绝缘中间层上。 在绝缘中间层上除去非化学吸附在绝缘中间层上的其余的钽胺衍生物。 将反应气体引入到绝缘中间层上。 化学吸附在绝缘中间层上的钽胺衍生物中的配体通过反应气体和配位体之间的化学反应从钽胺衍生物中除去以形成包括氮化钽的固体材料。 通过重复上述处理，将固体材料积聚在绝缘层间，形成布线。

公开(公告)号：US20050009336A1

公开(公告)日：2005-01-13

申请号：US10812768

申请日：2004-03-30

申请人： Jung-Hun Seo ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Hee-Sook Park

发明人： Jung-Hun Seo ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Hee-Sook Park

IPC分类号： H01L21/205 ,  C23C16/44 ,  C23C16/54 ,  H01L21/44 ,  H01L21/768

CPC分类号： C23C16/4408 ,  C23C16/54 ,  H01L21/76838 ,  H01L21/76841 ,  H01L21/76861

摘要： A metal deposition processing apparatus includes a first processing chamber configured for holding a semiconductor substrate therein. A second processing chamber is configured for holding the semiconductor substrate therein and for forming an upper metal layer thereon. A transfer chamber is connected to the first processing chamber and the second processing chamber. The transfer chamber is configured to transfer the semiconductor substrate between the first processing chamber and the second processing chamber.

摘要翻译： 金属沉积处理装置包括：第一处理室，被构造成用于将半导体基板保持在其中。 第二处理室构造成用于将半导体衬底保持在其中并用于在其上形成上金属层。 传送室连接到第一处理室和第二处理室。 传送室配置成在第一处理室和第二处理室之间传送半导体衬底。