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    METHOD AND APPARATUS FOR ENABLING A PROCESSOR TO GENERATE PIPELINE CONTROL SIGNALS
    42.
    发明申请
    METHOD AND APPARATUS FOR ENABLING A PROCESSOR TO GENERATE PIPELINE CONTROL SIGNALS 有权
    使用处理器生成管道控制信号的方法和装置

    公开(公告)号：US20150220342A1

    公开(公告)日：2015-08-06

    申请号：US14539104

    申请日：2014-11-12

    Applicant: Optimum Semiconductor Technologies, Inc.

    Inventor： C. John Glossner ,  Gary J. Nacer ,  Murugappan Senthilvelan ,  Vitaly Kalashnikov ,  Arthur J. Hoane ,  Paul D'Arcy ,  Sabin D. Iancu ,  Shenghong Wang

    IPC: G06F9/30 ,  G06F9/38

    CPC classification number: G06F9/3822 ,  G06F9/3836 ,  G06F9/3853

    Abstract: A chaining bit decoder of a computer processor receives an instruction stream. The chaining bit decoder selects a group of instructions from the instruction stream. The chaining bit decoder extracts a designated bit from each instruction of the instruction stream to produce a sequence of chaining bits. The chaining bit decoder decodes the sequence of chaining bits. The chaining bit decoder identifies zero or more instruction stream dependencies among the selected group of instructions in view of the decoded sequence of chaining bits. The chaining bit decoder outputs control signals to cause one or more pipelines stages of the processor to execute the selected group of instructions in view of the identified zero or more instruction stream dependencies among the group sequence of instructions.

    Abstract translation: 计算机处理器的链接位解码器接收指令流。 链接位解码器从指令流中选择一组指令。 链接位解码器从指令流的每个指令中提取指定的位以产生一系列链接位。 链接位解码器解码链接序列。 考虑到解码的链接序列，链接位解码器识别所选择的指令组之中的零个或多个指令流相关性。 链接位解码器输出控制信号以使得处理器的一个或多个管线级鉴于所述组指令序列中所识别的零个或多个指令流依赖性来执行所选择的指令组。

    VECTOR INSTRUCTION WITH PRECISE INTERRUPTS AND/OR OVERWRITES
    43.
    发明公开
    VECTOR INSTRUCTION WITH PRECISE INTERRUPTS AND/OR OVERWRITES 审中-公开

    公开(公告)号：US20230350688A1

    公开(公告)日：2023-11-02

    申请号：US18350729

    申请日：2023-07-11

    Applicant: Optimum Semiconductor Technologies Inc.

    Inventor： Mayan MOUDGILL ,  John GLOSSNER

    IPC: G06F9/38 ,  G06F9/30

    CPC classification number: G06F9/3857 ,  G06F9/30101 ,  G06F9/3861 ,  G06F9/3869

    Abstract: A processor includes a vector register file including vector registers, at least one buffer register, and a vector processing core to receive a vector instruction comprising a first identifier representing a first vector register of the vector registers, and a second identifier representing a second vector register of the vector registers, wherein the first vector register is a source register and the second vector register is a destination register, execute the vector instruction based on data values stored in the first vector register to generate a result and store the result in the at least one buffer register, and copy the result from the at least one buffer register to the second vector register.

    SYSTEM AND METHOD TO IMPLEMENT MASKED VECTOR INSTRUCTIONS
    45.
    发明申请
    SYSTEM AND METHOD TO IMPLEMENT MASKED VECTOR INSTRUCTIONS 有权

    公开(公告)号：US20220179653A1

    公开(公告)日：2022-06-09

    申请号：US17276598

    申请日：2019-09-18

    Applicant: Optimum Semiconductor Technologies Inc.

    Inventor： Mayan MOUDGILL ,  Murugappan SENTHILVELAN

    IPC: G06F9/30

    Abstract: A processor includes a register file comprising a length register, a vector register file comprising a plurality of vector registers, a mask register file comprising a plurality of mask registers, and a vector instruction execution circuit to execute a masked vector instruction comprising a first length register identifier representing the length register, a first vector register identifier representing a first vector register of the vector register file, and a first mask register identifier representing a first mask register of the mask register file, wherein the length register is to store a length value representing a number of operations to be applied to data elements stored in the first vector register, the first mask register is to store a plurality of mask bits, and a first mask bit of the plurality of mask bits determines whether a corresponding first one of the operations causes an effect.

    SYSTEM AND ARCHITECTURE NEURAL NETWORK ACCELERATOR INCLUDING FILTER CIRCUIT
    47.
    发明申请
    SYSTEM AND ARCHITECTURE NEURAL NETWORK ACCELERATOR INCLUDING FILTER CIRCUIT 有权

    公开(公告)号：US20220108148A1

    公开(公告)日：2022-04-07

    申请号：US17351425

    申请日：2021-06-18

    Applicant: Optimum Semiconductor Technologies Inc.

    Inventor： Mayan MOUDGILL ,  John GLOSSNER

    IPC: G06N3/04 ,  G06F9/30 ,  G06F9/38

    Abstract: A system and an accelerator circuit includes an internal memory to store data received a memory associated with a processor and a filter circuit block comprising a plurality of circuit stripes, each circuit stripe including a filter processor, a plurality of filter circuits, and a slice of the internal memory assigned to the plurality of filter circuits, where the filter processor is to execute a filter instruction to read data values from the internal memory based on a first memory address, for each of the plurality of circuit stripes: load the data values in weight registers and input registers associated with the plurality of filter circuits of the circuit stripe to generate a plurality of filter results, and write a result generated using the plurality of filter circuits in the internal memory at a second memory address.

    SYSTEM AND ARCHITECTURE INCLUDING PROCESSOR AND NEURAL NETWORK ACCELERATOR
    48.
    发明申请
    SYSTEM AND ARCHITECTURE INCLUDING PROCESSOR AND NEURAL NETWORK ACCELERATOR 有权

    公开(公告)号：US20210319284A1

    公开(公告)日：2021-10-14

    申请号：US17351434

    申请日：2021-06-18

    Applicant: Optimum Semiconductor Technologies Inc.

    Inventor： Mayan MOUDGILL ,  John GLOSSNER

    IPC: G06N3/04 ,  G06F9/30 ,  G06F9/38

    Abstract: A system and method include an accelerator circuit comprising an input circuit block, a filter circuit block, a post-processing circuit block, and an output circuit block and a processor to initialize the accelerator circuit, determining tasks of a neural network application to be performed by at least one of the input circuit block, the filter circuit block, the post-processing circuit block, or the output circuit block, assign each of the tasks to a corresponding one of the input circuit block, the filter circuit block, the post-processing circuit block, or the output circuit block, instruct the accelerator circuit to perform the tasks, and execute the neural network application based on results received from the accelerator circuit completing performance of the tasks.

    Processor with mode support
    50.
    发明授权
    Processor with mode support 有权

    公开(公告)号：US10908909B2

    公开(公告)日：2021-02-02

    申请号：US15155570

    申请日：2016-05-16

    Applicant: Optimum Semiconductor Technologies, Inc.

    Inventor： Mayan Moudgill ,  Gary Nacer ,  C. John Glossner ,  Arthur Joseph Hoane ,  Paul Hurtley ,  Murugappan Senthilvelan

    IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48 ,  G06F9/455

    Abstract: A computer processor may include a plurality of hardware threads. The computer processor may further include state processor logic for a state of a hardware thread. The state processor logic may include per thread logic that contains state that is replicated in each hardware thread of the plurality of hardware threads and common logic that is independent of each hardware thread of the plurality of hardware threads. The computer processor may further include single threaded mode logic to execute instructions in a single threaded mode from only one hardware thread of the plurality of hardware threads. The computer processor may further include second mode logic to execute instructions in a second mode from more than one hardware thread of the plurality of hardware threads simultaneously. The computer processor may further include switching mode logic to switch between the first mode and the second mode.

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