公开(公告)号：US08970262B2

公开(公告)日：2015-03-03

申请号：US13978373

申请日：2012-01-09

申请人： Rolf Weis ,  Franz Hirler ,  Martin Feldtkeller ,  Gerald Deboy ,  Matthias Stecher ,  Armin Willmeroth

发明人： Rolf Weis ,  Franz Hirler ,  Martin Feldtkeller ,  Gerald Deboy ,  Matthias Stecher ,  Armin Willmeroth

IPC分类号： H03B1/00 ,  H03K3/00 ,  H01L27/088 ,  H03K17/06 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/423 ,  H01L27/098 ,  H01L29/06

CPC分类号： H01L27/0207 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0623 ,  H01L27/0629 ,  H01L27/0727 ,  H01L27/088 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/098 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/78 ,  H01L29/7817 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7835 ,  H01L29/7838 ,  H03K17/06

摘要： Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

摘要翻译： 公开了一种包括具有负载路径的第一半导体器件和多个第二晶体管的半导体器件布置，每个第二晶体管具有在第一和第二负载端子与控制端子之间的负载路径。 第二晶体管的负载路径串联连接并与第一晶体管的负载路径串联连接，每个第二晶体管的控制端连接到其它第二晶体管之一的负载端，第二晶体管中的一个 晶体管的控制端子连接到第一半导体器件的负载端子之一。

公开(公告)号：US20140062544A1

公开(公告)日：2014-03-06

申请号：US13978373

申请日：2012-01-09

申请人： Rolf Weis ,  Franz Hirler ,  Martin Feldtkeller ,  Gerald Deboy ,  Matthias Stecher ,  Armin Willmeroth

发明人： Rolf Weis ,  Franz Hirler ,  Martin Feldtkeller ,  Gerald Deboy ,  Matthias Stecher ,  Armin Willmeroth

IPC分类号： H01L27/088 ,  H03K17/06

CPC分类号： H01L27/0207 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0623 ,  H01L27/0629 ,  H01L27/0727 ,  H01L27/088 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/098 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/78 ,  H01L29/7817 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7835 ,  H01L29/7838 ,  H03K17/06

摘要： Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

摘要翻译： 公开了一种包括具有负载路径的第一半导体器件和多个第二晶体管的半导体器件布置，每个第二晶体管具有在第一和第二负载端子与控制端子之间的负载路径。 第二晶体管的负载路径串联连接并与第一晶体管的负载路径串联连接，每个第二晶体管的控制端连接到其它第二晶体管之一的负载端，第二晶体管中的一个 晶体管的控制端子连接到第一半导体器件的负载端子之一。

公开(公告)号：US20120175635A1

公开(公告)日：2012-07-12

申请号：US13275151

申请日：2011-10-17

申请人： Rolf Weis ,  Franz Hirler ,  Matthias Stecher ,  Armin Willmeroth ,  Gerald Deboy ,  Martin Feldtkeller

发明人： Rolf Weis ,  Franz Hirler ,  Matthias Stecher ,  Armin Willmeroth ,  Gerald Deboy ,  Martin Feldtkeller

IPC分类号： H01L27/06 ,  H01L29/778 ,  H01L29/788 ,  H01L29/20 ,  H01L29/161 ,  H01L27/088 ,  H01L27/098

CPC分类号： H01L27/0207 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0623 ,  H01L27/0629 ,  H01L27/0727 ,  H01L27/088 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/098 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/78 ,  H01L29/7817 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7835 ,  H01L29/7838 ,  H03K17/06

摘要： A semiconductor device arrangement includes a first semiconductor device having a load path, and a number of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor. Each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors. One of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

摘要翻译： 半导体器件布置包括具有负载路径的第一半导体器件和多个第二晶体管，每个具有第一和第二负载端子与控制端子之间的负载路径。 第二晶体管的负载路径串联连接并与第一晶体管的负载路径串联连接。 每个第二晶体管的控制端连接到其它第二晶体管的负载端子。 第二晶体管中的一个具有其控制端子连接到第一半导体器件的负载端子之一。

公开(公告)号：US07973362B2

公开(公告)日：2011-07-05

申请号：US11866662

申请日：2007-10-03

申请人： Armin Willmeroth ,  Michael Rueb ,  Carolin Tolksdorf ,  Markus Schmitt

发明人： Armin Willmeroth ,  Michael Rueb ,  Carolin Tolksdorf ,  Markus Schmitt

IPC分类号： H01L29/66 ,  H01L27/088

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402

摘要： A semiconductor component includes a semiconductor body having an edge with an edge zone of a first conductivity type. Charge compensation regions of a second conductivity type are embedded into the edge zone, with the charge compensation regions extending from a top side of the semiconductor component vertically into the semiconductor body. For the number Ns of charge carriers present in a volume Vs between two charge compensation regions that are adjacent in a direction perpendicular to the edge, and for the number Np of charge carriers present in a volume Vp between two charge compensation regions that are adjacent in a direction parallel to the edge, Np>Ns holds true.

摘要翻译： 半导体部件包括具有边缘的第一导电类型的边缘区域的半导体本体。 第二导电类型的电荷补偿区域被嵌入到边缘区域中，电荷补偿区域从半导体组件的顶侧垂直延伸到半导体本体中。 对于在垂直于边缘的方向上相邻的两个电荷补偿区域之间存在的体积Vs中的电荷载流子数Ns以及存在于相邻的两个电荷补偿区域之间的体积Vp中的载流子数Np 与边缘平行的方向，Np> Ns成立。

公开(公告)号：US07821064B2

公开(公告)日：2010-10-26

申请号：US11276782

申请日：2006-03-14

申请人： Michael Rueb ,  Markus Schmitt ,  Carolin Tolksdorf ,  Uwe Wahl ,  Armin Willmeroth

发明人： Michael Rueb ,  Markus Schmitt ,  Carolin Tolksdorf ,  Uwe Wahl ,  Armin Willmeroth

IPC分类号： H01L29/00

CPC分类号： H01L29/782 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/7825

摘要： A lateral MISFET having a semiconductor body has a doped semiconductor substrate of a first conduction type and an epitaxial layer of a second conduction type, which is complementary to the first conduction type, the epitaxial layer being provided on the semiconductor substrate. This MISFET has, on the top side of the semiconductor body, a drain, a source, and a gate electrode with gate insulator. A semiconductor zone of the first conduction type is embedded in the epitaxial layer in a manner adjoining the gate insulator, a drift zone of the second conduction type being arranged between the semiconductor zone and the drain electrode in the epitaxial layer. The drift zone has pillar-type regions which are arranged in rows and columns and whose boundary layers have a metal layer which in each case forms a Schottky contact with the material of the drift zone.

摘要翻译： 具有半导体本体的横向MISFET具有第一导电类型的掺杂半导体衬底和与第一导电类型互补的第二导电类型的外延层，外延层设置在半导体衬底上。 该MISFET在半导体本体的顶侧具有漏极，源极和具有栅极绝缘体的栅电极。 第一导电类型的半导体区域以与栅极绝缘体相邻的方式嵌入在外延层中，第二导电类型的漂移区被布置在外延层中的半导体区域和漏极之间。 漂移区具有排列成行和列的柱状区域，其边界层具有金属层，其在每种情况下与漂移区的材料形成肖特基接触。

公开(公告)号：US20100181627A1

公开(公告)日：2010-07-22

申请号：US12355369

申请日：2009-01-16

申请人： Armin Willmeroth ,  Carolin Tolksdorf

发明人： Armin Willmeroth ,  Carolin Tolksdorf

IPC分类号： H01L27/06 ,  H01L21/02 ,  H01L23/522

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L27/0207 ,  H01L27/0629 ,  H01L28/20 ,  H01L2224/05552 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05691 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device and method for manufacturing. One embodiment provides a semiconductor device including an active cell region and a gate pad region. A conductive gate layer is arranged in the active cell region and a conductive resistor layer is arranged in the gate pad region. The resistor layer includes a resistor region which includes a grid-like pattern of openings formed in the resistor layer. A gate pad metallization is arranged at least partially above the resistor layer and in electrical contact with the resistor layer. An electrical connection is formed between the gate layer and the gate pad metallization, wherein the electrical connection includes the resistor region.

摘要翻译： 一种半导体器件及其制造方法。 一个实施例提供了包括有源电池区域和栅极焊盘区域的半导体器件。 导电栅极层布置在有源单元区域中，并且导电电阻层布置在栅极焊盘区域中。 电阻层包括电阻器区域，其包括形成在电阻层中的格栅状的开口。 栅极焊盘金属化至少部分地布置在电阻器层的上方并与电阻层电接触。 在栅极层和栅极焊盘金属化之间形成电连接，其中电连接包括电阻器区域。

公开(公告)号：US08324686B2

公开(公告)日：2012-12-04

申请号：US12355369

申请日：2009-01-16

申请人： Armin Willmeroth ,  Carolin Tolksdorf

发明人： Armin Willmeroth ,  Carolin Tolksdorf

IPC分类号： H01L27/12 ,  H01L21/20

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L27/0207 ,  H01L27/0629 ,  H01L28/20 ,  H01L2224/05552 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05691 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device and method for manufacturing. One embodiment provides a semiconductor device including an active cell region and a gate pad region. A conductive gate layer is arranged in the active cell region and a conductive resistor layer is arranged in the gate pad region. The resistor layer includes a resistor region which includes a grid-like pattern of openings formed in the resistor layer. A gate pad metallization is arranged at least partially above the resistor layer and in electrical contact with the resistor layer. An electrical connection is formed between the gate layer and the gate pad metallization, wherein the electrical connection includes the resistor region.

摘要翻译： 一种半导体器件及其制造方法。 一个实施例提供了包括有源电池区域和栅极焊盘区域的半导体器件。 导电栅极层布置在有源单元区域中，并且导电电阻层布置在栅极焊盘区域中。 电阻层包括电阻器区域，其包括形成在电阻层中的格栅状的开口。 栅极焊盘金属化至少部分地布置在电阻器层的上方并与电阻层电接触。 在栅极层和栅极焊盘金属化之间形成电连接，其中电连接包括电阻器区域。

公开(公告)号：US20080237701A1

公开(公告)日：2008-10-02

申请号：US11866662

申请日：2007-10-03

申请人： Armin Willmeroth ,  Michael Rueb ,  Carolin Tolksdorf ,  Markus Schmitt

发明人： Armin Willmeroth ,  Michael Rueb ,  Carolin Tolksdorf ,  Markus Schmitt

IPC分类号： H01L29/76 ,  H01L21/425

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402

摘要： A semiconductor component includes a semiconductor body having an edge with an edge zone of a first conductivity type. Charge compensation regions of a second conductivity type are embedded into the edge zone, with the charge compensation regions extending from a top side of the semiconductor component vertically into the semiconductor body. For the number Ns of charge carriers present in a volume Vs between two charge compensation regions that are adjacent in a direction perpendicular to the edge, and for the number Np of charge carriers present in a volume Vp between two charge compensation regions that are adjacent in a direction parallel to the edge, Np>Ns holds true.

摘要翻译： 半导体部件包括具有边缘的第一导电类型的边缘区域的半导体本体。 第二导电类型的电荷补偿区域被嵌入到边缘区域中，电荷补偿区域从半导体组件的顶侧垂直延伸到半导体本体中。 对于在垂直于边缘的方向上相邻的两个电荷补偿区域之间存在的体积V S s中存在的电荷载体的数量N SUB，以及数字N < 在与边缘平行的方向上相邻的两个电荷补偿区域之间存在于体积V p p中的电荷载体的SUB> p N N _成立。

公开(公告)号：US20060261384A1

公开(公告)日：2006-11-23

申请号：US11276782

申请日：2006-03-14

申请人： Michael Rueb ,  Markus Schmitt ,  Carolin Tolksdorf ,  Uwe Wahl ,  Armin Willmeroth

发明人： Michael Rueb ,  Markus Schmitt ,  Carolin Tolksdorf ,  Uwe Wahl ,  Armin Willmeroth

IPC分类号： H01L29/76

CPC分类号： H01L29/782 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/7825

摘要： A lateral MISFET having a semiconductor body has a doped semiconductor substrate of a first conduction type and an epitaxial layer of a second conduction type, which is complementary to the first conduction type, the epitaxial layer being provided on the semiconductor substrate. This MISFET has, on the top side of the semiconductor body, a drain, a source, and a gate electrode with gate insulator. A semiconductor zone of the first conduction type is embedded in the epitaxial layer in a manner adjoining the gate insulator, a drift zone of the second conduction type being arranged between the semiconductor zone and the drain electrode in the epitaxial layer. The drift zone has pillar-type regions which are arranged in rows and columns and whose boundary layers have a metal layer which in each case forms a Schottky contact with the material of the drift zone.

摘要翻译： 具有半导体本体的横向MISFET具有第一导电类型的掺杂半导体衬底和与第一导电类型互补的第二导电类型的外延层，外延层设置在半导体衬底上。 该MISFET在半导体本体的顶侧具有漏极，源极和具有栅极绝缘体的栅电极。 第一导电类型的半导体区域以与栅极绝缘体相邻的方式嵌入在外延层中，第二导电类型的漂移区被布置在外延层中的半导体区域和漏极之间。 漂移区具有排列成行和列的柱状区域，其边界层具有金属层，其在每种情况下与漂移区的材料形成肖特基接触。

公开(公告)号：US20070176229A1

公开(公告)日：2007-08-02

申请号：US11623571

申请日：2007-01-16

申请人： Armin Willmeroth ,  Holger Kapels

发明人： Armin Willmeroth ,  Holger Kapels

IPC分类号： H01L29/76

CPC分类号： H01L29/7816 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/7802 ,  H01L29/7824

摘要： An integrated circuit and component is disclosed. In one embodiment, the component is a compensation component, configuring the compensation regions in the drift zone in V-shaped fashion in order to achieve a convergence of the space charge zones from the upper to the lower end of the compensation regions is disclosed.

摘要翻译： 公开了一种集成电路和部件。 在一个实施例中，组件是补偿部件，公开了以V形方式构造漂移区域中的补偿区域，以实现空间电荷区域从补偿区域的上端到下端的会聚。