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72 条记录 (耗时 0.035 秒)

    Digital signal processing circuit having a SIMD circuit
    43.
    发明申请
    Digital signal processing circuit having a SIMD circuit 有权
    具有SIMD电路的数字信号处理电路

    公开(公告)号：US20060288069A1

    公开(公告)日：2006-12-21

    申请号：US11433331

    申请日：2006-05-12

    申请人： James Simkins ,  Jennifer Wong ,  Bernard New ,  Alvin Ching ,  John Thendean ,  Anna Wong ,  Vasisht Vadi

    发明人： James Simkins ,  Jennifer Wong ,  Bernard New ,  Alvin Ching ,  John Thendean ,  Anna Wong ,  Vasisht Vadi

    IPC分类号： G06F7/38

    CPC分类号： G06F7/02 ,  G06F7/5443 ,  G06F7/57 ,  G06F7/575 ,  G06F2207/025 ,  G06F2207/3828 ,  G06K9/00986 ,  H03K19/1737

    摘要： An Integrated Circuit (IC) having a single-instruction-multiple-data (SIMD) is disclosed. The SIMD circuit includes: a plurality of multiplexers controlled by a first opcode; and an arithmetic logic unit (ALU) coupled to the plurality of multiplexers and controlled by a second opcode; and wherein the ALU has a plurality of adders, where the plurality of adders are controlled by some bits of the second opcode, and where a first adder of the plurality of adders adds a plurality of input bits to produce first summation bits and a first carry bit; the first adder operating concurrently with the other adders of the plurality of adders.

    摘要翻译： 公开了具有单指令多数据（SIMD）的集成电路（IC）。 SIMD电路包括：由第一操作码控制的多个多路复用器; 以及耦合到所述多个多路复用器并由第二操作码控制的算术逻辑单元（ALU）; 并且其中所述ALU具有多个加法器，其中所述多个加法器由所述第二操作码的某些位控制，并且其中所述多个加法器中的第一加法器添加多个输入位以产生第一求和位和第一进位 位 所述第一加法器与所述多个加法器的其它加法器同时运行。

    Digital signal processing circuit having an adder circuit with carry-outs
    45.
    发明申请
    Digital signal processing circuit having an adder circuit with carry-outs 有权
    数字信号处理电路具有进位输出的加法电路

    公开(公告)号：US20060230096A1

    公开(公告)日：2006-10-12

    申请号：US11433517

    申请日：2006-05-12

    申请人： John Thendean ,  Jennifer Wong ,  Bernard New ,  Alvin Ching ,  James Simkins ,  Anna Wong ,  Vasisht Vadi

    发明人： John Thendean ,  Jennifer Wong ,  Bernard New ,  Alvin Ching ,  James Simkins ,  Anna Wong ,  Vasisht Vadi

    IPC分类号： G06F7/50

    CPC分类号： G06F7/02 ,  G06F7/5443 ,  G06F7/57 ,  G06F7/575 ,  G06F2207/025 ,  G06F2207/3828 ,  G06K9/00986 ,  H03K19/1737

    摘要： An integrated circuit having a digital signal processing (DSP) circuit is disclosed. The DSP circuit includes: a plurality of multiplexers receiving a first set, second set, and third set of input data bits, where the plurality of multiplexers are coupled to a first opcode register; a bitwise adder coupled to the plurality of multiplexers for generating a sum set of bits and a carry set of bits from bitwise adding together the first, second, and third set of input data bits; and a second adder coupled to the bitwise adder for adding together the sum set of bits and carry set of bits to produce a summation set of bits and a plurality of carry-out bits, where the second adder is coupled to a second opcode register.

    摘要翻译： 公开了一种具有数字信号处理（DSP）电路的集成电路。 DSP电路包括：多个多路复用器，其接收第一组，第二组和第三组输入数据位，其中多个复用器耦合到第一操作码寄存器; 耦合到所述多个多路复用器的按位加法器，用于从所述第一，第二和第三输入数据位组合中逐位地生成位组和位的进位组; 以及第二加法器，其耦合到所述按位加法器，用于将所述位的总和相加和进位位组，以产生位和和多个进位位的求和集合，其中所述第二加法器耦合到第二操作码寄存器。

    Programmable logic device with decryption and structure for preventing design relocation
    47.
    发明授权
    Programmable logic device with decryption and structure for preventing design relocation 有权
    具有解密和结构的可编程逻辑器件，用于防止设计重新定位

    公开(公告)号：US07117372B1

    公开(公告)日：2006-10-03

    申请号：US09724972

    申请日：2000-11-28

    申请人： Stephen M. Trimberger ,  Raymond C. Pang ,  Walter N. Sze ,  Jennifer Wong

    发明人： Stephen M. Trimberger ,  Raymond C. Pang ,  Walter N. Sze ,  Jennifer Wong

    IPC分类号： H04L9/14 ,  H04K1/00

    CPC分类号： G01R31/31719 ,  G06F12/1408 ,  G06F21/76 ,  H04L9/0625 ,  H04L9/0637

    摘要： It is sometimes desirable to protect a design used in a PLD from being copied. According to the present invention, the design is encrypted, then loaded into a PLD, then decrypted, and then loaded into the configuration memory of the PLD. An attacker could relocate the design to a visible part of the PLD and learn the design. The present invention prevents design relocation by attaching address information to the encryption key or by encrypting an address where the design is to be loaded as well as encrypting the design itself. Thus, if an attacker tries to load the design into a different part of the PLD, the encrypted design will not decrypt properly.

    摘要翻译： 有时期望保护PLD中使用的设计不被复制。 根据本发明，设计被加密，然后加载到PLD中，然后解密，然后加载到PLD的配置存储器中。 攻击者可以将设计重新定位到PLD的可见部分，并学习设计。 本发明通过将地址信息附加到加密密钥或通过加密设计要加载的地址以及加密设计本身来防止设计重定位。 因此，如果攻击者试图将设计加载到PLD的不同部分，则加密的设计将无法正确解密。

    Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks
    48.
    发明授权
    Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks 有权
    在逻辑块阵列中提供紧密耦合的处理器和RAM块列的结构和方法

    公开(公告)号：US06946874B1

    公开(公告)日：2005-09-20

    申请号：US10927750

    申请日：2004-08-27

    申请人： Goran Bilski ,  Ralph D. Wittig ,  Jennifer Wong ,  David B. Squires

    发明人： Goran Bilski ,  Ralph D. Wittig ,  Jennifer Wong ,  David B. Squires

    IPC分类号： G06F15/78 ,  H03K19/177 ,  H03K19/0177

    CPC分类号： H03K19/1776 ,  G06F15/7867 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/17796

    摘要： Structures and methods of including processor capabilities in an existing PLD architecture with minimal disruption to the existing general interconnect structure. In a PLD including a column of block RAM (BRAM) blocks, the BRAM blocks are modified to create specialized logic blocks including a RAM, a processor, and a dedicated interface coupled between the RAM, the processor, and the general interconnect structure of the PLD. The additional area is obtained by increasing the width of the column of BRAM blocks. Because the interconnect structure remains virtually unchanged, the interconnections between the specialized logic blocks and the adjacent tiles are already in place, and the modifications do not affect the PLD routing software. In some embodiments, the processor can be optionally disabled, becoming transparent to the user. Other embodiments provide methods of modifying a PLD to include the structures and provide the capabilities described above.

    摘要翻译： 在现有PLD架构中包含处理器能力的结构和方法，对现有的一般互连结构的影响最小。 在包括块RAM（BRAM）块的PLD中，BRAM块被修改以创建专用逻辑块，包括RAM，处理器和耦合在RAM，处理器和通用互连结构之间的专用接口 PLD。 通过增加BRAM块的列的宽度来获得附加区域。 由于互连结构几乎保持不变，所以专用逻辑块和相邻的瓦片之间的互连已经就位，并且修改不会影响PLD路由软件。 在一些实施例中，处理器可以可选地被禁用，对于用户变得透明。 其他实施例提供了修改PLD以包括结构并提供上述能力的方法。