公开(公告)号：US5496764A

公开(公告)日：1996-03-05

申请号：US270542

申请日：1994-07-05

申请人： Shih-Wei Sun

发明人： Shih-Wei Sun

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76264 ,  H01L21/76275 ,  H01L21/76283 ,  Y10S148/012 ,  Y10S148/135

摘要： An insulating layer is formed over a first substrate. Trenches are formed within a second substrate, and those trenches are filled with an insulating layer. The two substrate are bonded at their insulating layers. The portion of the second substrate away from the trenches is removed to form semiconductor regions over the insulating layer of the first substrate. Embodiments of the present invention allow better thickness control for SOI regions and lower leakage current compared to SOI layers that use LOCOS-type field isolation.

摘要翻译： 在第一基板上形成绝缘层。 沟槽形成在第二基板内，并且那些沟槽被填充绝缘层。 两个基板在它们的绝缘层上结合。 去除第二衬底远离沟槽的部分，以在第一衬底的绝缘层上形成半导体区域。 与使用LOCOS型场隔离的SOI层相比，本发明的实施例允许SOI区域更好的厚度控制和更低的漏电流。

公开(公告)号：US5406111A

公开(公告)日：1995-04-11

申请号：US205477

申请日：1994-03-04

申请人： Shih-Wei Sun

发明人： Shih-Wei Sun

IPC分类号： H01L27/02 ,  H01L29/90 ,  H01L21/265

CPC分类号： H01L27/0251

摘要： An input/output protection device for an integrated circuit is formed using a trench (22). A first electrode region (46) is formed adjacent a first portion of the trench sidewall (24), and a second electrode region (48) is formed adjacent a second portion of the trench sidewall (24). One of the electrode regions is then electrically coupled to an input/output pad, while the other electrode region is electrically coupled to ground. Excessive voltages on the input/output pad are then discharged when the electrode, which is electrically coupled to the input/output pad, punches through to the electrode that is electrically coupled to ground.

摘要翻译： 使用沟槽（22）形成用于集成电路的输入/输出保护装置。 在沟槽侧壁（24）的第一部分附近形成第一电极区域（46），并且邻近沟槽侧壁（24）的第二部分形成第二电极区域（48）。 然后电极区域中的一个电耦合到输入/输出焊盘，而另一个电极区域电耦合到地。 当电耦合到输入/输出焊盘的电极穿过电耦合到地的电极时，输出/输出焊盘上的过大的电压被放电。

公开(公告)号：US07615434B2

公开(公告)日：2009-11-10

申请号：US11389617

申请日：2006-03-24

申请人： Shih-Wei Sun ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao ,  Pei-Yu Chou

发明人： Shih-Wei Sun ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao ,  Pei-Yu Chou

IPC分类号： H01L21/8238

CPC分类号： H01L21/823864 ,  H01L21/823807 ,  H01L29/7843

摘要： A CMOS device is provided, comprising a substrate, a first-type MOS transistor, a second-type MOS transistor, a first stress layer, a first liner layer, and a second stress layer. The substrate has a first active area and a second active area, which are separated by an isolation structure. Further, the first-type MOS transistor is disposed on the first active area of the substrate, and the second-type MOS transistor is disposed on the second active area of the substrate. The first stress layer is compliantly disposed on the first-type MOS transistor of the first active area. The first liner layer is compliantly disposed on the first stress layer. The second stress layer is compliantly disposed on the second-type MOS transistor of the second active area.

摘要翻译： 提供一种CMOS器件，包括衬底，第一类型MOS晶体管，第二类型MOS晶体管，第一应力层，第一衬里层和第二应力层。 衬底具有由隔离结构隔开的第一有源区和第二有源区。 此外，第一型MOS晶体管设置在衬底的第一有源区上，并且第二型MOS晶体管设置在衬底的第二有源区上。 第一应力层顺应地设置在第一有源区的第一型MOS晶体管上。 第一衬里层顺应地设置在第一应力层上。 第二应力层顺从地设置在第二有源区的第二型MOS晶体管上。

公开(公告)号：US07078346B2

公开(公告)日：2006-07-18

申请号：US10902315

申请日：2004-07-29

申请人： Chih-Chien Liu ,  Ta-Shan Tseng ,  Wen-Bin Shieh ,  Juan-Yuan Wu ,  Water Lur ,  Shih-Wei Sun

发明人： Chih-Chien Liu ,  Ta-Shan Tseng ,  Wen-Bin Shieh ,  Juan-Yuan Wu ,  Water Lur ,  Shih-Wei Sun

IPC分类号： H01L21/311

CPC分类号： H01L21/02112 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/0276 ,  H01L21/31612 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76838

摘要： A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.

公开(公告)号：US06492732B2

公开(公告)日：2002-12-10

申请号：US09849666

申请日：2001-05-04

申请人： Ellis Lee ,  Shih-Wei Sun

发明人： Ellis Lee ,  Shih-Wei Sun

IPC分类号： H01L23522

CPC分类号： H01L21/7682 ,  H01L21/76802

摘要： An interconnect structure has a substrate having devices already formed thereon. A dielectric layer covers over the substrate. A conductive structure having at least two substructure separated by an air gap is formed on the dielectric layer. A capping layer covers the conductive structure and the air gap. The capping layer at a portion above the air gap also fills into the air gap by a predetermined distance. The air gap may also extend into the dielectric layer to have a greater height. An etching stop layer is formed on the capping layer. An inter-metal dielectric layer is formed on the etching stop layer. The inter-metal dielectric layer, the etching stop layer and the capping layer are patterned to form an opening that exposes a top surface of the conductive structure. The opening may also expose a top portion of a sidewall of the conductive structure if a misalignment occurs, but the opening does not expose the air gap due to protection from the predetermined distance of the capping layer within the air gap. A next level of conductive structure can be formed to fill the opening. A liner layer can be also formed on a sidewall of the substructure interfacing the air gap, so as to protect the conductive structure.

摘要翻译： 互连结构具有其上已经形成有器件的衬底。 电介质层覆盖在衬底上。 在电介质层上形成具有至少两个由气隙分隔的子结构的导电结构。 覆盖层覆盖导电结构和气隙。 在气隙上方的一部分上的覆盖层也填充到气隙中预定的距离。 气隙也可以延伸到电介质层中以具有更大的高度。 在覆盖层上形成蚀刻停止层。 在蚀刻停止层上形成金属间介电层。 将金属间介电层，蚀刻停止层和覆盖层图案化以形成露出导电结构的顶表面的开口。 如果发生不对准，则开口也可能暴露出导电结构的侧壁的顶部部分，但是由于防止气隙内的封盖层的预定距离的保护，开口不暴露气隙。 可以形成下一级的导电结构以填充开口。 衬垫层也可以形成在与气隙接合的子结构的侧壁上，以便保护导电结构。

公开(公告)号：US06492256B2

公开(公告)日：2002-12-10

申请号：US10098718

申请日：2002-03-15

申请人： Ellis Lee ,  Shih-Wei Sun

发明人： Ellis Lee ,  Shih-Wei Sun

IPC分类号： H01L214763

CPC分类号： H01L21/7682 ,  H01L21/76802

摘要： An interconnect structure has a substrate having devices already formed thereon. A dielectric layer covers over the substrate. A conductive structure having at least two substructure separated by an air gap is formed on the dielectric layer. A capping layer covers the conductive structure and the air gap. The capping layer at a portion above the air gap also fills into the air gap by a predetermined distance. The air gap may also extend into the dielectric layer to have a greater height. An etching stop layer is formed on the capping layer. An inter-metal dielectric layer is formed on the etching stop layer. The inter-metal dielectric layer, the etching stop layer and the capping layer are patterned to form an opening that exposes a top surface of the conductive structure. The opening may also expose a top portion of a sidewall of the conductive structure if a misalignment occurs, but the opening does not expose the air gap due to protection from the predetermined distance of the capping layer within the air gap. A next level of conductive structure can be formed to fill the opening. A liner layer can be also formed on a sidewall of the substructure interfacing the air gap, so as to protect the conductive structure.

摘要翻译： 互连结构具有其上已经形成有器件的衬底。 电介质层覆盖在衬底上。 在电介质层上形成具有至少两个由气隙隔开的子结构的导电结构。 覆盖层覆盖导电结构和气隙。 在气隙上方的一部分上的覆盖层也填充到气隙中预定的距离。 气隙也可以延伸到电介质层中以具有更大的高度。 在覆盖层上形成蚀刻停止层。 在蚀刻停止层上形成金属间介电层。 将金属间介电层，蚀刻停止层和覆盖层图案化以形成露出导电结构的顶表面的开口。 如果发生不对准，则开口也可能暴露出导电结构的侧壁的顶部部分，但是由于防止气隙内的封盖层的预定距离的保护，开口不暴露气隙。 可以形成下一级的导电结构以填充开口。 衬垫层也可以形成在与气隙接合的子结构的侧壁上，以便保护导电结构。

公开(公告)号：US06245380B1

公开(公告)日：2001-06-12

申请号：US09249582

申请日：1999-02-11

申请人： Shih-Wei Sun ,  Wen-Yi Hsieh ,  Water Lur ,  Kun-Chih Wang

发明人： Shih-Wei Sun ,  Wen-Yi Hsieh ,  Water Lur ,  Kun-Chih Wang

IPC分类号： B05D512

CPC分类号： H01L24/05 ,  H01L21/76807 ,  H01L21/76847 ,  H01L21/76877 ,  H01L24/03 ,  H01L24/11 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05546 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00014

摘要： A method of forming bonding pad commences by forming a conformal barrier layer on a provided inter-metal dielectric layer. A first metal layer is formed on the barrier layer to partially fill the trench. A thin glue layer is formed on the first metal layer. A second metal layer is formed on the glue layer to fill the trench. The second metal layer, the glue layer, the first metal layer and the barrier layer are partially removed to expose the dielectric layer. A bonding pad structure is thus formed in the trench. The bonding pad structure comprises a first metal pad and a second metal pad.

摘要翻译： 通过在所提供的金属间介电层上形成保形阻挡层，开始形成焊盘的方法。 在阻挡层上形成第一金属层以部分地填充沟槽。 在第一金属层上形成薄胶层。 在胶层上形成第二金属层以填充沟槽。 部分去除第二金属层，胶层，第一金属层和阻挡层，以露出介质层。 因此在沟槽中形成接合焊盘结构。 焊盘结构包括第一金属焊盘和第二金属焊盘。

公开(公告)号：US06203863B1

公开(公告)日：2001-03-20

申请号：US09200893

申请日：1998-11-27

申请人： Chih-Chien Liu ,  Juan-Yuan Wu ,  Water Lur ,  Shih-Wei Sun

发明人： Chih-Chien Liu ,  Juan-Yuan Wu ,  Water Lur ,  Shih-Wei Sun

IPC分类号： B05D306

CPC分类号： H01L21/02164 ,  C23C16/045 ,  C23C16/50 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31612 ,  H01L21/76834 ,  H01L21/76837

摘要： A method of gap filling by using HDPCVD. On a substrate having a conductive structure, a first oxide layer is formed to protect the conductive structure. While forming the first oxide layer no bias is applied. An argon flow with a high speed of etching/deposition is provided to form a second oxide layer. While forming the second oxide layer a triangular or trapezium profile is formed due to an etching effect to the corner. An argon flow with a low speed of etching/deposition is provided to form a third oxide layer. The gap filling is completed.

摘要翻译： 使用HDPCVD的间隙填充方法。 在具有导电结构的基板上形成第一氧化物层以保护导电结构。 当形成第一氧化物层时，不施加偏压。 提供具有高速蚀刻/沉积的氩气流以形成第二氧化物层。 在形成第二氧化物层的同时，由于对拐角的蚀刻效果，形成三角形或梯形轮廓。 提供具有低速蚀刻/沉积的氩气流以形成第三氧化物层。 间隙填充完成。

公开(公告)号：US6153459A

公开(公告)日：2000-11-28

申请号：US192643

申请日：1998-11-16

申请人： Shih-Wei Sun

发明人： Shih-Wei Sun

IPC分类号： H01L21/8242 ,  H01L21/8244

CPC分类号： H01L27/10873 ,  H01L27/10894

摘要： A method of fabricating a dual gate of embedded DRAM forms a conductive layer on a substrate having a memory cell region and a logic circuitry. A gate structure is then formed on the substrate of the memory cell region and the conductive layer of the logic circuitry is removed by patterning the conductive layer. A polysilicon layer is then deposited and a dual gate structure is formed by patterning the polysilicon layer, and simultaneously, a polysilicon spacer is formed on the sidewall of the gate structure in the logic circuitry. The polysilicon spacer is then removed. An insulated spacer is formed on the sidewall of the gate structure and the dual gate structure, and a silicide layer is formed on the dual gate structure and the exposed substrate of the logic circuitry.

摘要翻译： 制造嵌入式DRAM的双栅极的方法在具有存储单元区域和逻辑电路的衬底上形成导电层。 然后在存储单元区域的衬底上形成栅极结构，并且通过图案化导电层来去除逻辑电路的导电层。 然后沉积多晶硅层，并且通过图案化多晶硅层形成双栅极结构，同时，在逻辑电路中的栅极结构的侧壁上形成多晶硅间隔物。 然后去除多晶硅间隔物。 在栅极结构和双栅极结构的侧壁上形成绝缘间隔物，并且在双栅极结构和逻辑电路的暴露的衬底上形成硅化物层。

公开(公告)号：US06114200A

公开(公告)日：2000-09-05

申请号：US996697

申请日：1997-12-23

申请人： Tri-Rung Yew ,  Water Lur ,  Shih-Wei Sun

发明人： Tri-Rung Yew ,  Water Lur ,  Shih-Wei Sun

IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L21/8242 ,  H01L21/20

CPC分类号： H01L27/10852 ,  H01L28/60

摘要： A method of fabricating a DRAM device to reduce the stress and enhance the adhesion between the top electrode and the interlevel dielectric layer, includes forming a titanium layer between the top electrode and the interlevel dielectric layer. A titanium oxide layer and a titanium silicide are formed between the titanium layer and the interlevel dielectric layer in post thermal procedures, which enhances the adhesion and avoids cracks and leakage current between the top electrode and the interlevel dielectric layer.

摘要翻译： 一种制造DRAM器件以减少应力并增强顶部电极和层间电介质层之间的粘附性的方法包括在顶部电极和层间电介质层之间形成钛层。 在后热工程中，在钛层和层间电介质层之间形成氧化钛层和硅化钛，这增强了附着力，避免了顶部电极和层间电介质层之间的裂纹和漏电流。