公开(公告)号：US20060220149A1

公开(公告)日：2006-10-05

申请号：US11092227

申请日：2005-03-28

申请人： Bomy Chen ,  Kevin Jew

发明人： Bomy Chen ,  Kevin Jew

IPC分类号： H01L29/76

CPC分类号： G11C27/005 ,  G11C16/10

摘要： An integrated circuit programmable resistor or programmable capacitor has a floating gate memory cell connected either in series or in parallel to a fixed resistor or a fixed capacitor. The resistance or the capacitance of the floating gate memory cell can be changed by the amount of charge stored on the floating gate which affects the resistance or the capacitance of the channel from which the floating gate is spaced apart. A particular application of the programmable resistor/capacitor is used in a system whereby the resistance or the capacitance can be change or fine tuned as a result of either drift caused by time or by operating conditions such as temperature. Thus, the temperature of the substrate in which the floating gate memory cell is fabricated can be monitored and the resistance or the capacitance of the floating gate memory cell changed dynamically.

摘要翻译： 集成电路可编程电阻器或可编程电容器具有与固定电阻器或固定电容器串联或并联连接的浮动栅极存储器单元。 可以通过浮动栅极上存储的电荷量来改变浮动栅极存储单元的电阻或电容，影响浮动栅极间隔开的沟道的电阻或电容。 可编程电阻器/电容器的特定应用在系统中使用，由此由于由时间引起的漂移或诸如温度的操作条件导致的电阻或电容可以改变或微调。 因此，可以监视其中制造浮动栅极存储单元的衬底的温度，并且动态地改变浮动栅极存储单元的电阻或电容。

公开(公告)号：US06937507B2

公开(公告)日：2005-08-30

申请号：US10729605

申请日：2003-12-05

申请人： Bomy Chen

发明人： Bomy Chen

IPC分类号： G11C11/00 ,  G11C16/02 ,  H01L27/24

CPC分类号： G11C13/004 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0078 ,  G11C2213/72 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/2454 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/1666

摘要： An array of phase changing memory cells that includes a current source, a voltage sensor, a plurality of conductive bit lines electrically connected to the current source, a plurality of conductive word lines each electrically connected to a ground plane via a first resistor and to the voltage sensor, and a plurality of memory cells. Each memory cell is connected between one of the bit lines and one of the word lines and includes phase change memory material. One of the memory cells is selected by turning on switches just on the bit line and word line connected thereto, or by turning a switch connected in series between the corresponding bit and word lines, where the read current flows through the selected memory cell and the voltage sensor measures a voltage drop across the selected memory cell.

摘要翻译： 一种相变存储器单元的阵列，包括电流源，电压传感器，电连接到电流源的多个导电位线，多个导电字线，每个导电字线经由第一电阻器电连接到接地层， 电压传感器和多个存储单元。 每个存储单元连接在一个位线和一条字线之间，并且包括相变存储器材料。 其中一个存储单元是通过接通开关位于与其连接的位线和字线上，或者通过将串联连接在相应的位和字线之间的开关转换开来来选择的，其中读取的电流流过选定的存储单元， 电压传感器测量所选存储单元上的电压降。

公开(公告)号：US07701248B2

公开(公告)日：2010-04-20

申请号：US12100406

申请日：2008-04-10

申请人： Kai Man Yue ,  Bomy Chen ,  Geeng Chuan Michael Chern ,  Tsung-Lu Syu

发明人： Kai Man Yue ,  Bomy Chen ,  Geeng Chuan Michael Chern ,  Tsung-Lu Syu

IPC分类号： G06F7/38 ,  H03K19/173 ,  G11C7/00

CPC分类号： H03K17/693 ,  G11C16/0433 ,  G11C16/26

摘要： The present invention is a storage element for controlling a logic circuit and a logic device having a plurality of storage elements. The storage element has a first and a second non-volatile memory cells connected in series at an output node. Each of the first and second non-volatile memory cells is for storing a state opposite to the other. A demultiplexer has an input, a switched input and two outputs. The output node is connected to the input of the demultiplexer. One of the outputs is used to control the logic circuit. The other output is connected to a bit line which is connected to a sense amplifier. Finally, the switched input receives a switch signal and outputs the signal from the output node to either the one output or the other output.

摘要翻译： 本发明是用于控制逻辑电路的存储元件和具有多个存储元件的逻辑器件。 存储元件具有在输出节点串联连接的第一和第二非易失性存储器单元。 第一和第二非易失性存储单元中的每一个用于存储与另一个相反的状态。 解复用器具有输入，开关输入和两个输出。 输出节点连接到解复用器的输入端。 其中一个输出用于控制逻辑电路。 另一个输出连接到连接到读出放大器的位线。 最后，切换输入接收开关信号，并将输出节点的信号输出到一个输出或另一个输出。

公开(公告)号：US07403418B2

公开(公告)日：2008-07-22

申请号：US11241582

申请日：2005-09-30

申请人： Ya-Fen Lin ,  Elbert Lin ,  Hieu Van Tran ,  Jack Edward Frayer ,  Bomy Chen

发明人： Ya-Fen Lin ,  Elbert Lin ,  Hieu Van Tran ,  Jack Edward Frayer ,  Bomy Chen

IPC分类号： G11C11/34

CPC分类号： G11C8/08 ,  G11C16/08

摘要： A first embodiment of a word line voltage boosting circuit for use with an array of non-volatile memory cells has a capacitor, having two ends, connected to the word line. One end of the capacitor is electrically connected to the word line. The other end of the capacitor is electrically connected to a first voltage source. The word line is also connected through a switch to a second source voltage source. A sequencing circuit activates the switch such that the word line is connected to the second voltage source, and the other end of the capacitor is not connected to the first voltage source. Then the sequencing circuit causes the switch to disconnect the word line from the second voltage source, and connect the second end of the capacitor to the first voltage source. The alternate switching of the connection boosts the voltage on the word line. In a second embodiment, a first word line is electrically connected to a first switch to a first voltage source. An adjacent word line, capacitively coupled to the first word line, is electrically connected to a second switch to a second voltage source. A sequencing circuit activates the first switch and the second switch such that the first word line is connected to the first voltage source, and the second word line is disconnected from the second voltage source. Then the sequencing circuit causes the first switch to disconnect the first word line from the first voltage source, and causes the second word line to be electrically connected to the second voltage source. The alternate switching of the connection boosts the voltage on the first word line, caused by its capacitive coupling to the second word line. A boosted voltage on the word line may be used to improve cycling and yield, where the memory cells of the array are of the floating gate type and erase through the mechanism of Fowler-Nordheim tunneling from the floating gate to a control gate which is connected to the word line.

公开(公告)号：US07351613B2

公开(公告)日：2008-04-01

申请号：US10983314

申请日：2004-11-04

申请人： Bomy Chen ,  Ya-Fen Lin ,  Zhitang Song ,  Songlin Feng

发明人： Bomy Chen ,  Ya-Fen Lin ,  Zhitang Song ,  Songlin Feng

IPC分类号： H01L21/82

CPC分类号： H01L28/20 ,  H01C17/267 ,  H01L22/22

摘要： A method of trimming down the volume of a semiconductor resistor element using electrical resistance feedback. After forming conductive material disposed between a pair of electrodes, a voltage is applied to the electrodes to produce an electrical current through the conductive material sufficient to heat and melt away a portion of the conductive material. By reducing the volume of the conductive material, its resistance is increased. The application of the voltage is ceased once the desired dimensions (and thus resistivity) of the conductive material is reached. The resulting semiconductor resistor element could have a fixed resistance, or could have a variable resistance (by using phase change memory material).

摘要翻译： 使用电阻反馈来减少半导体电阻元件的体积的方法。 在形成设置在一对电极之间的导电材料之后，向电极施加电压以产生通过导电材料的电流，足以加热和熔化掉导电材料的一部分。 通过减小导电材料的体积，其电阻增加。 一旦达到导电材料的所需尺寸（因此电阻率），电压的施加就会停止。 所得到的半导体电阻元件可以具有固定电阻，或者可以具有可变电阻（通过使用相变存储器材料）。

公开(公告)号：US20070007581A1

公开(公告)日：2007-01-11

申请号：US11520993

申请日：2006-09-14

申请人： Bomy Chen ,  Sohrab Kianian ,  Yaw Hu

发明人： Bomy Chen ,  Sohrab Kianian ,  Yaw Hu

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/7885

摘要： A memory cell has a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the trench and a second portion extending horizontally along the substrate surface. An electrically conductive floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. An electrically conductive control gate is disposed over and insulated from the channel region second portion. An erase gate is disposed in the trench adjacent to and insulated from the floating gate. A block of conductive material has at least a lower portion thereof disposed in the trench adjacent to and insulated from the erase gate, and electrically connected to the source region.

摘要翻译： 存储单元具有形成在半导体衬底的表面中的沟槽，以及在其间形成沟道区的间隔开的源极和漏极区。 源极区形成在沟槽下方，并且沟道区域包括沿着沟槽的侧壁垂直延伸的第一部分和沿衬底表面水平延伸的第二部分。 导电浮置栅极设置在沟槽中，与沟道区域第一部分相邻并与其绝缘。 导电控制栅极设置在沟道区第二部分之上并与沟道区第二部分绝缘。 擦除栅极设置在与浮动栅极相邻并与浮栅绝缘的沟槽中。 一块导电材料至少有一个下部设置在沟槽中，与沟槽相邻并与擦除栅绝缘，并与源极区电连接。

公开(公告)号：US20050199914A1

公开(公告)日：2005-09-15

申请号：US11070079

申请日：2005-03-01

申请人： Bomy Chen ,  Ying Tsui ,  Wen-Juei Lu

发明人： Bomy Chen ,  Ying Tsui ,  Wen-Juei Lu

IPC分类号： H01L27/10 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L29/73

CPC分类号： H01L27/11556 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7885

摘要： A method of forming an array of floating gate memory cells, and an array formed thereby, wherein a trench is formed into a surface of a semiconductor substrate. The source region is formed underneath the trench, the drain region is formed along the substrate surface, and the channel region therebetween includes a first portion extending vertically along the trench sidewall and a second portion extending horizontally along the substrate surface. The floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. The control gate is disposed over and insulated from the channel region second portion. The trench sidewall meets the substrate surface at an acute angle to form a sharp edge. The channel region second portion extends from the second region in a direction toward the sharp edge and the floating gate to define a path for programming the floating gate with electrons via hot electron injection.

摘要翻译： 一种形成浮置栅极存储单元阵列的方法，以及由此形成的阵列，其中沟槽形成在半导体衬底的表面中。 源极区形成在沟槽下方，漏极区沿着衬底表面形成，并且其间的沟道区包括沿着沟槽侧壁垂直延伸的第一部分和沿衬底表面水平延伸的第二部分。 浮动栅极设置在与沟道区域第一部分相邻并与沟槽区域第一部分绝缘的沟槽中。 控制栅极设置在通道区域第二部分之上并与沟道区域第二部分绝缘。 沟槽侧壁以锐角与衬底表面相接触以形成锋利的边缘。 沟道区域第二部分从朝向尖锐边缘的方向从第二区域延伸，并且浮置栅极限定用于通过热电子注入用电子编程浮动栅极的路径。

公开(公告)号：US06873006B2

公开(公告)日：2005-03-29

申请号：US10393896

申请日：2003-03-21

申请人： Bomy Chen ,  Ying Kit Tsui ,  Wen-Juei Lu

发明人： Bomy Chen ,  Ying Kit Tsui ,  Wen-Juei Lu

IPC分类号： H01L27/10 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11556 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7885

摘要： A method of forming an array of floating gate memory cells, and an array formed thereby, wherein a trench is formed into a surface of a semiconductor substrate. The source region is formed underneath the trench, the drain region is formed along the substrate surface, and the channel region therebetween includes a first portion extending vertically along the trench sidewall and a second portion extending horizontally along the substrate surface. The floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. The control gate is disposed over and insulated from the channel region second portion. The trench sidewall meets the substrate surface at an acute angle to form a sharp edge. The channel region second portion extends from the second region in a direction toward the sharp edge and the floating gate to define a path for programming the floating gate with electrons via hot electron injection.

摘要翻译： 一种形成浮置栅极存储单元阵列的方法，以及由此形成的阵列，其中沟槽形成在半导体衬底的表面中。 源极区形成在沟槽下方，漏极区沿着衬底表面形成，并且其间的沟道区包括沿着沟槽侧壁垂直延伸的第一部分和沿衬底表面水平延伸的第二部分。 浮动栅极设置在与沟道区域第一部分相邻并与沟槽区域第一部分绝缘的沟槽中。 控制栅极设置在通道区域第二部分之上并与沟道区域第二部分绝缘。 沟槽侧壁以锐角与衬底表面相接触以形成锋利的边缘。 沟道区域第二部分从朝向尖锐边缘的方向从第二区域延伸，并且浮置栅极限定用于通过热电子注入用电子编程浮动栅极的路径。

公开(公告)号：US06834009B1

公开(公告)日：2004-12-21

申请号：US10641803

申请日：2003-08-15

申请人： Kai Man Yue ,  Bomy Chen

发明人： Kai Man Yue ,  Bomy Chen

IPC分类号： G11C1604

CPC分类号： H03K19/17748 ,  H03K19/1778

摘要： A nonvolatile reprogrammable switch for use in a PLD or FPGA has a nonvolatile memory cell connected to the gate of an MOS transistor with the terminals of the MOS transistor connected to the source of the signal and to the circuit. The nonvolatile memory cell is of a split gate type having a first region and a second region, with a channel therebetween. The cell has a floating gate positioned over a first portion of the channel, which is adjacent to the first region and a control gate positioned over a second portion of the channel, which is adjacent to the second region. The second region is connected to the gate of the MOS transistor. The cell is programmed by injecting electrons from the channel onto the floating gate by hot electron injection mechanism. The cell is erased by Fowler-Nordheim tunneling of the electrons from the floating gate to the control gate. As a result, no high voltage is ever applied to the second region during program or erase. In addition a MOS FET transistor connects the gate of the MOS transistor to a voltage when the non-volatile memory cell is turned off. The floating gate of the non-volatile memory cell is connected to the gate of the MOS FET transistor.

摘要翻译： 用于PLD或FPGA的非易失性可重新编程开关具有连接到MOS晶体管的栅极的非易失性存储单元，MOS晶体管的端子连接到信号源和电路。 非易失性存储单元是具有第一区域和第二区域的分离栅极类型，其间具有沟道。 电池具有位于通道第一部分上方的浮动栅极，该第一部分与第一区域相邻，并且控制栅极位于与第二区域相邻的通道的第二部分上方。 第二区域连接到MOS晶体管的栅极。 通过热电子注入机制将电子从通道注入到浮动栅上来编程电池。 Fowler-Nordheim将电池从浮动栅极隧穿到控制栅极，从而消除电池。 因此，在编程或擦除期间，不会对第二区域施加高电压。 此外，MOS FET晶体管将MOS晶体管的栅极连接到非易失性存储单元关断时的电压。 非易失性存储单元的浮置栅极连接到MOS FET晶体管的栅极。

公开(公告)号：US06815704B1

公开(公告)日：2004-11-09

申请号：US10656486

申请日：2003-09-04

申请人： Bomy Chen

发明人： Bomy Chen

IPC分类号： H01L4700

CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/1666

摘要： A phase change memory device, and method of making the same, that includes contact holes formed in insulation material that extend down to and exposes source regions for adjacent FET transistors. Spacer material is disposed in the holes with surfaces that define openings each having a width that narrows along a depth of the opening. Lower electrodes are disposed in the holes. A layer of phase change material is disposed along the spacer material surfaces and along at least a portion of the lower electrodes. Upper electrodes are formed in the openings and on the phase change material layer. Voids are formed into the spacer material to impede heat from the phase change material from conducting through the insulation material. For each contact hole, the upper electrode and phase change material layer form an electrical current path that narrows in width as the current path approaches the lower electrode.

摘要翻译： 一种相变存储器件及其制造方法，包括形成在绝缘材料中的接触孔，该绝缘材料向下延伸并暴露相邻FET晶体管的源极区域。 间隔件材料设置在孔中，其表面限定开口，每个开口具有沿着开口的深度变窄的宽度。 下电极设置在孔中。 沿着间隔物材料表面和沿着下部电极的至少一部分设置一层相变材料。 上电极形成在开口和相变材料层上。 空隙形成间隔物材料以阻止相变材料的热量通过绝缘材料传导。 对于每个接触孔，上电极和相变材料层形成当电流路径接近下电极时宽度变窄的电流通路。