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    Radial self-propagation pattern generation for disk file servowriting
    41.
    发明授权
    Radial self-propagation pattern generation for disk file servowriting 失效
    用于磁盘文件伺服驱动的径向自传模式生成

    公开(公告)号：US5612833A

    公开(公告)日：1997-03-18

    申请号：US349028

    申请日：1994-12-02

    Applicant: Edward J. Yarmchuk ,  Mark D. Schultz ,  Bucknell C. Webb ,  Timothy J. Chainer

    Inventor： Edward J. Yarmchuk ,  Mark D. Schultz ,  Bucknell C. Webb ,  Timothy J. Chainer

    IPC: G11B5/012 ,  G11B5/55 ,  G11B5/596 ,  G11B21/10

    CPC classification number: G11B5/5534 ,  G11B21/10 ,  G11B21/106 ,  G11B5/59633 ,  G11B5/59644

    Abstract: During a write revolution of a storage medium, a transition is written on the storage medium while servoing on another transition previously recorded on the storage medium. During that write revolution, a position error signal corresponding to the position error of the transducer relative to the previously recorded transition is determined. That position error signal is then stored, during the write revolution, to be used in computing a reference track value associated with the transition being written to correct for the position error. Additionally, a product servo-pattern is written, which includes an embodying of the position error therein.

    Abstract translation: 在存储介质的写入转动期间，在先前记录在存储介质上的另一个转换上进行伺服处理，在存储介质上写入转换。 在该写入旋转期间，确定对应于换能器相对于先前记录的转变的位置误差的位置误差信号。 然后在写入旋转期间存储该位置误差信号，以用于计算与被写入的转换相关联的参考轨迹值，以校正位置误差。 此外，写入产品伺服图案，其中包括其中的位置误差。

    Semiconductor trench inductors and transformers
    43.
    发明授权
    Semiconductor trench inductors and transformers 有权
    半导体沟槽电感和变压器

    公开(公告)号：US08686522B2

    公开(公告)日：2014-04-01

    申请号：US13272485

    申请日：2011-10-13

    Applicant: Bucknell C. Webb

    Inventor： Bucknell C. Webb

    IPC: H01L29/82 ,  H01L21/02

    CPC classification number: H01L23/645 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Semiconductor trench inductor and transformer structures are provided, which include thin film conductive layers and magnetic layers formed within trenches etched in semiconductor substrates. Semiconductor trench devices effectively provide vertical oriented inductor and transformer structures whereby conductive coils and magnetic layers are vertically oriented on edge within trenches, thereby providing a space-saving compact design, and which allows the conductive layers within the trench to be enclosed by magnetic material, thereby providing a density of magnetic material that increases the storable energy density.

    Abstract translation: 提供半导体沟槽电感器和变压器结构，其包括形成在半导体衬底中蚀刻的沟槽内的薄膜导电层和磁性层。 半导体沟槽器件有效地提供垂直取向的电感器和变压器结构，由此导电线圈和磁性层在沟槽内的边缘垂直取向，从而提供节省空间的紧凑设计，并且允许沟槽内的导电层被磁性材料包围， 从而提供增加可储存能量密度的磁性材料的密度。

    INDUCTOR WITH STACKED CONDUCTORS
    44.
    发明申请
    INDUCTOR WITH STACKED CONDUCTORS 有权
    带导体的电感器

    公开(公告)号：US20130314192A1

    公开(公告)日：2013-11-28

    申请号：US13477978

    申请日：2012-05-22

    Applicant: Robert E. Fontana, JR. ,  Philipp Herget ,  Eugene J. O'Sullivan ,  Lubomyr T. Romankiw ,  Naigang Wang ,  Bucknell C. Webb

    Inventor： Robert E. Fontana, JR. ,  Philipp Herget ,  Eugene J. O'Sullivan ,  Lubomyr T. Romankiw ,  Naigang Wang ,  Bucknell C. Webb

    IPC: H01F27/28

    CPC classification number: H01F27/2804 ,  H01F5/00 ,  H01F17/0013 ,  H01F2017/0066 ,  H01F2017/0086 ,  H01F2027/2809 ,  H01L28/10

    Abstract: A thin film coupled inductor, a thin film spiral inductor, and a system that includes an electronic device and a power supply or power converter incorporating one or more such inductors. A thin film coupled inductor includes a wafer substrate; a bottom yoke comprising a magnetic material above the wafer substrate; a first insulating layer above the bottom yoke; a first conductor above the bottom yoke and separated therefrom by the first insulating layer; a second insulating layer above the first conductor; a second conductor above the second insulating layer; a third insulating layer above the second conductor; and a non-planar top yoke above the third insulating layer, the top yoke comprising a magnetic material.

    Abstract translation: 薄膜耦合电感器，薄膜螺旋电感器以及包括电子器件和并入一个或多个此类电感器的电源或功率转换器的系统。 薄膜耦合电感器包括晶片衬底; 底部轭，其包括晶片衬底上方的磁性材料; 在底部轭上方的第一绝缘层; 第一导体，位于底部磁轭之上并由第一绝缘层分离; 在所述第一导体上方的第二绝缘层; 在第二绝缘层上方的第二导体; 在第二导体上方的第三绝缘层; 以及在第三绝缘层上方的非平面顶部磁轭，顶部磁轭包括磁性材料。

    MAGNETIC WRITER HAVING MULTIPLE GAPS WITH MORE UNIFORM MAGNETIC FIELDS ACROSS THE GAPS
    47.
    发明申请
    MAGNETIC WRITER HAVING MULTIPLE GAPS WITH MORE UNIFORM MAGNETIC FIELDS ACROSS THE GAPS 有权
    具有更多均匀磁场的多个GAPS的磁性写作

    公开(公告)号：US20110102116A1

    公开(公告)日：2011-05-05

    申请号：US12611294

    申请日：2009-11-03

    Applicant: Robert G. Biskeborn ,  Philipp Herget ,  Bucknell C. Webb

    Inventor： Robert G. Biskeborn ,  Philipp Herget ,  Bucknell C. Webb

    IPC: H01F7/02

    CPC classification number: G11B5/3116 ,  G11B5/17 ,  G11B5/23 ,  G11B5/265 ,  G11B5/2652 ,  G11B5/59638

    Abstract: A magnetic device according to one embodiment includes a source of flux; a magnetic pole coupled to the source of flux, the magnetic pole having two or more gaps; and a low reluctance path positioned towards at least one of the gaps and not positioned towards at least one other of the gaps for affecting a magnetic field formed at the at least one of the gaps when the source of flux is generating flux. Other disclosed embodiments include devices having coil turns with a non-uniform placement in the magnetic yoke for altering a magnetic field formed at the at least one of the gaps during writing. In further embodiments, a geometry of the magnetic pole near or at one of the gaps is different than a geometry of the magnetic pole near or at another of the gaps to help equalize fields formed at the gaps when the source of flux is generating flux.

    Abstract translation: 根据一个实施例的磁性装置包括通量源; 耦合到磁通源的磁极，所述磁极具有两个或更多个间隙; 以及朝向所述间隙中的至少一个定位的低磁阻路径，并且朝向所述间隙中的至少另一个定位，以在所述通量源产生磁通时影响形成在所述至少一个间隙处的磁场。 其他公开的实施例包括具有在磁轭中具有不均匀布置的线圈匝的装置，用于在写入期间改变在至少一个间隙处形成的磁场。 在另外的实施例中，靠近或在其中一个间隙处的磁极的几何形状不同于磁极在靠近或另一个间隙处的几何形状，以帮助当磁通源产生磁通时在间隙处形成的场均衡。

    Through-wafer vias
    49.
    发明授权
    Through-wafer vias 有权
    通晶圆通孔

    公开(公告)号：US07741722B2

    公开(公告)日：2010-06-22

    申请号：US11690181

    申请日：2007-03-23

    Applicant: Paul Stephen Andry ,  Edmund Juris Sprogis ,  Kenneth Jay Stein ,  Timothy Dooling Sullivan ,  Cornelia Kang-I Tsang ,  Ping-Chuan Wang ,  Bucknell C. Webb

    Inventor： Paul Stephen Andry ,  Edmund Juris Sprogis ,  Kenneth Jay Stein ,  Timothy Dooling Sullivan ,  Cornelia Kang-I Tsang ,  Ping-Chuan Wang ,  Bucknell C. Webb

    IPC: H01L23/48

    CPC classification number: H01L23/481 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

    Abstract: A through-wafer via structure and method for forming the same. The through-wafer via structure includes a wafer having an opening and a top wafer surface. The top wafer surface defines a first reference direction perpendicular to the top wafer surface. The through-wafer via structure further includes a through-wafer via in the opening. The through-wafer via has a shape of a rectangular plate. A height of the through-wafer via in the first reference direction essentially equals a thickness of the wafer in the first reference direction. A length of the through-wafer via in a second reference direction is at least ten times greater than a width of the through-wafer via in a third reference direction. The first, second, and third reference directions are perpendicular to each other.

    Abstract translation: 一种晶片通孔结构及其形成方法。 贯通晶片通孔结构包括具有开口和顶部晶片表面的晶片。 顶部晶片表面限定垂直于顶部晶片表面的第一参考方向。 贯通晶片通孔结构还包括在开口中的通晶片通孔。 贯通晶片通孔具有矩形板的形状。 贯通晶片通孔在第一参考方向上的高度基本上等于晶片在第一参考方向上的厚度。 贯穿晶片通孔在第二参考方向上的长度比通过晶片通孔在第三参考方向上的宽度大至少十倍。 第一，第二和第三参考方向彼此垂直。

    THROUGH-WAFER VIAS
    50.
    发明申请
    THROUGH-WAFER VIAS 有权
    通过六角形

    公开(公告)号：US20080274583A1

    公开(公告)日：2008-11-06

    申请号：US11690181

    申请日：2007-03-23

    Applicant: Paul Stephen Andry ,  Edmund Juris Sprogis ,  Kenneth Jay Stein ,  Timothy Dooling Sullivan ,  Cornelia Kang-I Tsang ,  Ping-Chuan Wang ,  Bucknell C. Webb

    Inventor： Paul Stephen Andry ,  Edmund Juris Sprogis ,  Kenneth Jay Stein ,  Timothy Dooling Sullivan ,  Cornelia Kang-I Tsang ,  Ping-Chuan Wang ,  Bucknell C. Webb

    IPC: H01L21/00

    CPC classification number: H01L23/481 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

    Abstract: A through-wafer via structure and method for forming the same. The through-wafer via structure includes a wafer having an opening and a top wafer surface. The top wafer surface defines a first reference direction perpendicular to the top wafer surface. The through-wafer via structure further includes a through-wafer via in the opening. The through-wafer via has a shape of a rectangular plate. A height of the through-wafer via in the first reference direction essentially equals a thickness of the wafer in the first reference direction. A length of the through-wafer via in a second reference direction is at least ten times greater than a width of the through-wafer via in a third reference direction. The first, second, and third reference directions are perpendicular to each other.

    Abstract translation: 一种晶片通孔结构及其形成方法。 贯通晶片通孔结构包括具有开口和顶部晶片表面的晶片。 顶部晶片表面限定垂直于顶部晶片表面的第一参考方向。 贯通晶片通孔结构还包括在开口中的通晶片通孔。 贯通晶片通孔具有矩形板的形状。 贯通晶片通孔在第一参考方向上的高度基本上等于晶片在第一参考方向上的厚度。 贯穿晶片通孔在第二参考方向上的长度比通过晶片通孔在第三参考方向上的宽度大至少十倍。 第一，第二和第三参考方向彼此垂直。

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