公开(公告)号：US07829408B2

公开(公告)日：2010-11-09

申请号：US12429951

申请日：2009-04-24

申请人： Cheng-Chi Lin ,  Shin Su ,  Chien-Wen Chu ,  Shih-Chin Lien ,  Chin-Pen Yeh

发明人： Cheng-Chi Lin ,  Shin Su ,  Chien-Wen Chu ,  Shih-Chin Lien ,  Chin-Pen Yeh

IPC分类号： H01L21/8238

CPC分类号： H01L29/0847 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835

摘要： The present invention discloses a laterally double-diffused metal oxide semiconductor transistor (LDMOS) and a method for fabricating the same. The LDMOS includes a substrate, a first well, a drain, a second well and a source. The substrate includes a first conductive dopant. The first well includes a second conductive dopant and formed in a part of the substrate, and the drain is located in the first well. The second well includes the first conductive dopant and formed in another part of the substrate, and the source located in the second well. The source includes a lightly doped region and a heavily doped region extending downwardly from a top surface of the substrate. The depth of the lightly doped region is more than the depth of the heavily doped region.

摘要翻译： 本发明公开了一种横向双扩散金属氧化物半导体晶体管（LDMOS）及其制造方法。 LDMOS包括衬底，第一阱，漏极，第二阱和源极。 衬底包括第一导电掺杂剂。 第一阱包括第二导电掺杂剂并形成在衬底的一部分中，并且漏极位于第一阱中。 第二阱包括第一导电掺杂剂并且形成在衬底的另一部分中，并且源位于第二阱中。 源包括从衬底的顶表面向下延伸的轻掺杂区域和重掺杂区域。 轻掺杂区域的深度大于重掺杂区域的深度。

公开(公告)号：US20090209075A1

公开(公告)日：2009-08-20

申请号：US12429951

申请日：2009-04-24

申请人： Cheng-Chi LIN ,  Shin Su ,  Chein-Wen Chu ,  Shih-Chin Lien ,  Chin-Pen Yeh

发明人： Cheng-Chi LIN ,  Shin Su ,  Chein-Wen Chu ,  Shih-Chin Lien ,  Chin-Pen Yeh

IPC分类号： H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835

摘要： The present invention discloses a laterally double-diffused metal oxide semiconductor transistor (LDMOS) and a method for fabricating the same. The LDMOS includes a substrate, a first well, a drain, a second well and a source. The substrate includes a first conductive dopant. The first well includes a second conductive dopant and formed in a part of the substrate, and the drain is located in the first well. The second well includes the first conductive dopant and formed in another part of the substrate, and the source located in the second well. The source includes a lightly doped region and a heavily doped region extending downwardly from a top surface of the substrate. The depth of the lightly doped region is more than the depth of the heavily doped region.

摘要翻译： 本发明公开了一种横向双扩散金属氧化物半导体晶体管（LDMOS）及其制造方法。 LDMOS包括衬底，第一阱，漏极，第二阱和源极。 衬底包括第一导电掺杂剂。 第一阱包括第二导电掺杂剂并形成在衬底的一部分中，并且漏极位于第一阱中。 第二阱包括第一导电掺杂剂并且形成在衬底的另一部分中，并且源位于第二阱中。 源包括从衬底的顶表面向下延伸的轻掺杂区域和重掺杂区域。 轻掺杂区域的深度大于重掺杂区域的深度。

公开(公告)号：US07525153B2

公开(公告)日：2009-04-28

申请号：US11399427

申请日：2006-04-07

申请人： Cheng-Chi Lin ,  Shin Su ,  Chien-Wen Chu ,  Shih-Chin Lien ,  Chin-Pen Yeh

发明人： Cheng-Chi Lin ,  Shin Su ,  Chien-Wen Chu ,  Shih-Chin Lien ,  Chin-Pen Yeh

IPC分类号： H01L29/94

CPC分类号： H01L29/0847 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835

摘要： The present invention discloses a laterally double-diffused metal oxide semiconductor transistor (LDMOS) and a method for fabricating the same. The LDMOS includes a substrate, a first well, a drain, a second well and a source. The substrate includes a first conductive dopant. The first well includes a second conductive dopant and formed in a part of the substrate, and the drain is located in the first well. The second well includes the first conductive dopant and formed in another part of the substrate, and the source located in the second well. The source includes a lightly doped region and a heavily doped region extending downwardly from a top surface of the substrate. The depth of the lightly doped region is more than the depth of the heavily doped region.

摘要翻译： 本发明公开了一种横向双扩散金属氧化物半导体晶体管（LDMOS）及其制造方法。 LDMOS包括衬底，第一阱，漏极，第二阱和源极。 衬底包括第一导电掺杂剂。 第一阱包括第二导电掺杂剂并形成在衬底的一部分中，并且漏极位于第一阱中。 第二阱包括第一导电掺杂剂并且形成在衬底的另一部分中，并且源位于第二阱中。 源包括从衬底的顶表面向下延伸的轻掺杂区域和重掺杂区域。 轻掺杂区域的深度大于重掺杂区域的深度。

公开(公告)号：US20120146139A1

公开(公告)日：2012-06-14

申请号：US12962702

申请日：2010-12-08

申请人： Hsuehi Huang ,  Y.F. Huang ,  Shih-Chin Lien

发明人： Hsuehi Huang ,  Y.F. Huang ,  Shih-Chin Lien

IPC分类号： H01L29/78

CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66689

摘要： A semiconductor device for a high voltage application includes a doped source base region, an N+ source region, a P+ source region and a gate structure. The doped source base region has P-type. The N+ source region extends downwards into the doped source base region. The P+ source region is close to the N+ source region, extends downwards into the doped source base region, and is doped heavier than the doped source base region. The gate structure is coupled to the N+ source region and is near to the P+ source region.

摘要翻译： 用于高电压应用的半导体器件包括掺杂源极基极区域，N +源极区域，P +源极区域和栅极结构。 掺杂源极区具有P型。 N +源极区域向下延伸到掺杂源极基极区域中。 P +源极区域靠近N +源极区域，向下延伸到掺杂源极区域中，并且掺杂得比掺杂源极区域重。 栅极结构耦合到N +源极区并且靠近P +源极区。

公开(公告)号：US20110303977A1

公开(公告)日：2011-12-15

申请号：US12797896

申请日：2010-06-10

申请人： Yin-Fu Huang ,  Miao-Chun Chung ,  Shih-Chin Lien

发明人： Yin-Fu Huang ,  Miao-Chun Chung ,  Shih-Chin Lien

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

摘要： An LDPMOS structure having enhanced breakdown voltage and specific on-resistance is described, as is a method for fabricating the structure. A P-field implanted layer formed in a drift region of the structure and surrounding a lightly doped drain region effectively increases breakdown voltage while maintaining a relatively low specific on-resistance.

摘要翻译： 描述了具有增强的击穿电压和比导通电阻的LDPMOS结构，以及制造该结构的方法。 形成在该结构的漂移区域并围绕轻掺杂漏极区的P场注入层有效地增加了击穿电压，同时保持相对较低的比导通电阻。

公开(公告)号：US08507993B2

公开(公告)日：2013-08-13

申请号：US13596970

申请日：2012-08-28

申请人： Yin-Fu Huang ,  Ming Rong Chang ,  Shih-Chin Lien

发明人： Yin-Fu Huang ,  Ming Rong Chang ,  Shih-Chin Lien

IPC分类号： H01L27/092

CPC分类号： H01L29/7322 ,  H01L21/2652 ,  H01L21/324 ,  H01L21/761 ,  H01L29/0821 ,  H01L29/107 ,  H01L29/167 ,  H01L29/66272 ,  H01L29/78

摘要： Various aspects of the technology are directed to integrated circuit manufacturing methods and integrated circuits. In one method, a first charge type buried layer in a semiconductor material of an integrated circuit by implanting first charge type dopants of the first charge type buried layer through a sacrificial oxide over the semiconductor material and through an intermediate region of the semiconductor material transited by the implanted first charge type dopants. When the implanted dopants pass through the sacrificial oxide, damage to the semiconductor crystalline lattice is averted. If the sacrificial oxide were absent, the implanted dopants would have passed through and damaged the semiconductor crystalline lattice instead. Later, a pre-anneal oxide is grown and removed.

摘要翻译： 该技术的各个方面都针对集成电路制造方法和集成电路。 在一种方法中，集成电路的半导体材料中的第一电荷型掩埋层，其通过半导体材料上的牺牲氧化物并通过半导体材料的中间区域注入第一电荷型掩埋层的第一电荷型掺杂剂，并通过半导体材料的中间区域 植入的第一电荷型掺杂剂。 当注入的掺杂剂通过牺牲氧化物时，避免对半导体晶格的损伤。 如果牺牲氧化物不存在，则注入的掺杂剂将已经通过并损坏半导体晶格。 之后，生长并除去预退火氧化物。

公开(公告)号：US08476705B2

公开(公告)日：2013-07-02

申请号：US12962702

申请日：2010-12-08

申请人： Hsuehi Huang ,  Yin-Fu Huang ,  Shih-Chin Lien

发明人： Hsuehi Huang ,  Yin-Fu Huang ,  Shih-Chin Lien

IPC分类号： H01L29/78

CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66689

摘要： A semiconductor device for a high voltage application includes a doped source base region, an N+ source region, a P+ source region and a gate structure. The doped source base region has P-type. The N+ source region extends downwards into the doped source base region. The P+ source region is close to the N+ source region, extends downwards into the doped source base region, and is doped heavier than the doped source base region. The gate structure is coupled to the N+ source region and is near to the P+ source region.

摘要翻译： 用于高电压应用的半导体器件包括掺杂源极基极区域，N +源极区域，P +源极区域和栅极结构。 掺杂源极区具有P型。 N +源极区域向下延伸到掺杂源极基极区域中。 P +源极区域靠近N +源极区域，向下延伸到掺杂源极区域中，并且掺杂得比掺杂源极区域重。 栅极结构耦合到N +源极区并且靠近P +源极区。

公开(公告)号：US20130037883A1

公开(公告)日：2013-02-14

申请号：US13648964

申请日：2012-10-10

申请人： Yin-Fu Huang ,  Miao-Chun Chung ,  Shih-Chin Lien

发明人： Yin-Fu Huang ,  Miao-Chun Chung ,  Shih-Chin Lien

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

摘要： An LDPMOS structure having enhanced breakdown voltage and specific on-resistance is described, as is a method for fabricating the structure. A P-field implanted layer formed in a drift region of the structure and surrounding a tightly doped drain region effectively increases breakdown voltage while maintaining a relatively low specific on-resistance.

摘要翻译： 描述了具有增强的击穿电压和比导通电阻的LDPMOS结构，以及制造该结构的方法。 形成在该结构的漂移区并围绕紧密掺杂的漏极区的P场注入层有效地增加击穿电压，同时保持相对较低的比导通电阻。

公开(公告)号：US20110049677A1

公开(公告)日：2011-03-03

申请号：US12549869

申请日：2009-08-28

申请人： Yin-Fu Huang ,  Ming Rong Chang ,  Shih-Chin Lien

发明人： Yin-Fu Huang ,  Ming Rong Chang ,  Shih-Chin Lien

IPC分类号： H01L29/06 ,  H01L21/761

CPC分类号： H01L29/7322 ,  H01L21/2652 ,  H01L21/324 ,  H01L21/761 ,  H01L29/0821 ,  H01L29/107 ,  H01L29/167 ,  H01L29/66272 ,  H01L29/78

摘要： Various aspects of the technology are directed to integrated circuit manufacturing methods and integrated circuits. In one method, a first charge type buried layer in a semiconductor material of an integrated circuit by implanting first charge type dopants of the first charge type buried layer through a sacrificial oxide over the semiconductor material and through an intermediate region of the semiconductor material transited by the implanted first charge type dopants. When the implanted dopants pass through the sacrificial oxide, damage to the semiconductor crystalline lattice is averted. If the sacrificial oxide were absent, the implanted dopants would have passed through and damaged the semiconductor crystalline lattice instead. Later, a pre-anneal oxide is grown and removed.

摘要翻译： 该技术的各个方面都针对集成电路制造方法和集成电路。 在一种方法中，通过在半导体材料上通过牺牲氧化物并通过半导体材料的中间区域注入第一电荷型掩埋层的第一电荷型掺杂剂，并通过半导体材料的中间区域转移集成电路的半导体材料中的第一电荷型掩埋层 植入的第一电荷型掺杂剂。 当注入的掺杂剂通过牺牲氧化物时，避免对半导体晶格的损伤。 如果牺牲氧化物不存在，则注入的掺杂剂将已经通过并损坏半导体晶格。 之后，生长并除去预退火氧化物。

公开(公告)号：US08357547B2

公开(公告)日：2013-01-22

申请号：US13538455

申请日：2012-06-29

申请人： Ming-Tung Lee ,  Shih-Chin Lien ,  Chia-Huan Chang

发明人： Ming-Tung Lee ,  Shih-Chin Lien ,  Chia-Huan Chang

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： G01N33/525 ,  G01N27/4145 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor bio-sensor comprises providing a substrate, forming a first dielectric layer on the substrate, forming a patterned first conductive layer on the first dielectric layer, the patterned first conductive layer including a first portion and a pair of second portions, forming a second dielectric layer, a third dielectric layer and a fourth dielectric layer in sequence over the patterned first conductive layer, forming cavities into the fourth dielectric layer, forming vias through the cavities, exposing the second portions of the patterned first conductive layer, forming a patterned second conductive layer on the fourth dielectric layer, forming a passivation layer on the patterned second conductive layer, forming an opening to expose a portion of the third dielectric layer over the first portion of the patterned first conductive layer, and forming a chamber through the opening.

摘要翻译： 制造半导体生物传感器的方法包括：提供衬底，在衬底上形成第一介电层，在第一电介质层上形成图案化的第一导电层，图案化的第一导电层包括第一部分和一对第二部分 在所述图案化的第一导电层上依次形成第二电介质层，第三电介质层和第四电介质层，在所述第四电介质层中形成空腔，形成通过所述空腔的通孔，暴露所述图案化的第一导电层的第二部分， 在所述第四电介质层上形成图案化的第二导电层，在所述图案化的第二导电层上形成钝化层，形成开口，以暴露所述图案化的第一导电层的所述第一部分上的所述第三电介质层的一部分， 通过开放。