利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

77 条记录 (耗时 0.035 秒)

    Method of forming self-aligned poly for embedded flash
    41.
    发明授权
    Method of forming self-aligned poly for embedded flash 有权
    用于嵌入式闪光灯的自对准聚酰亚胺的方法

    公开(公告)号：US07153744B2

    公开(公告)日：2006-12-26

    申请号：US10822505

    申请日：2004-04-12

    申请人： Han-Ping Chen ,  Chung-Yi Yu

    发明人： Han-Ping Chen ,  Chung-Yi Yu

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11534 ,  H01L27/1203 ,  H01L29/42324 ,  H01L29/7885

    摘要： A method of manufacturing a microelectronic device including, in one embodiment, providing a substrate having a plurality of partially completed microelectronic devices including at least one partially completed memory device and at least one partially completed transistor. At least a portion of the partially completed transistor is protected by forming a first layer over the portion of the partially completed transistor to be protected during a subsequent material removal step. A second layer is formed substantially covering the partially completed memory device and the partially completed transistor. Portions of the second layer are removed leaving a portion of the second layer over the partially completed memory device. At least a substantial portion of the first layer is removed from the partially completed transistor after the portions of the second layer are removed.

    摘要翻译： 一种制造微电子器件的方法，在一个实施例中包括提供具有多个部分完成的微电子器件的衬底，所述微电子器件包括至少一个部分完成的存储器件和至少一个部分完成的晶体管。 通过在随后的材料去除步骤期间在待保护的部分完成的晶体管的部分上形成第一层来保护部分完成的晶体管的至少一部分。 形成基本覆盖部分完成的存储器件和部分完成的晶体管的第二层。 去除第二层的部分，留下部分完成的存储器件上的第二层的一部分。 在去除第二层的部分之后，第一层的至少大部分被从部分完成的晶体管中去除。

    Image sensor with light guides
    42.
    发明申请
    Image sensor with light guides 有权
    带导光板的图像传感器

    公开(公告)号：US20060014314A1

    公开(公告)日：2006-01-19

    申请号：US11229655

    申请日：2005-09-20

    申请人： Dun-Nian Yaung ,  Chung-Yi Yu

    发明人： Dun-Nian Yaung ,  Chung-Yi Yu

    IPC分类号： H01L21/00

    CPC分类号： H01L27/14685 ,  H01L27/1462 ,  H01L27/14623 ,  H01L27/14625

    摘要： An image sensor device and fabrication method thereof. An image sensing array is formed in a substrate, wherein the image sensing array comprises a plurality of photosensors with spaces therebetween. A first dielectric layer with a first refractive index is formed overlying the spaces but not the photosensors. A conformal second dielectric layer with a second refractive index is formed on a sidewall of the first dielectric layer. A third dielectric layer with a third refractive index is formed overlying the photosensors but not the spaces. The third refractive index is greater than the second refractive index. A light guide constructed by the second and third dielectric layers is formed overlying each photosensor, thereby preventing incident light from striking other photosensors.

    摘要翻译： 一种图像传感器装置及其制造方法。 图像感测阵列形成在基板中，其中图像感测阵列包括在其间具有间隔的多个光电传感器。 具有第一折射率的第一介电层形成在空间上而不是光电传感器上。 在第一介电层的侧壁上形成具有第二折射率的共形的第二介电层。 形成具有第三折射率的第三介电层，覆盖光电传感器而不是空间。 第三折射率大于第二折射率。 由第二和第三电介质层构成的导光体形成在每个光电传感器上，从而防止入射光撞击其他感光体。

    Method of forming MIM capacitor electrodes
    43.
    发明申请
    Method of forming MIM capacitor electrodes 有权
    形成MIM电容器电极的方法

    公开(公告)号：US20050215004A1

    公开(公告)日：2005-09-29

    申请号：US10811657

    申请日：2004-03-29

    申请人： Chih-Ta Wu ,  Kuo-Yin Lin ,  Tsung-Hsun Huang ,  Chung-Yi Yu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Hsing-Lien Lin ,  Chia-Shiung Tsai

    发明人： Chih-Ta Wu ,  Kuo-Yin Lin ,  Tsung-Hsun Huang ,  Chung-Yi Yu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Hsing-Lien Lin ,  Chia-Shiung Tsai

    IPC分类号： H01G4/005 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/44 ,  H01L23/522 ,  H01L29/06

    CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A novel method for forming electrodes in the fabrication of an MIM (metal-insulator-metal) capacitor, is disclosed. The method improves MIM capacitor performance by preventing plasma-induced damage to a dielectric layer during deposition of a top electrode on the dielectric layer, as well as by reducing or preventing the formation of an interfacial layer between the dielectric layer and the electrode or electrodes, in fabrication of the MIM capacitor. The method typically includes the patterning of crown-type capacitor openings in a substrate; depositing a bottom electrode in each of the crown openings; subjecting the bottom electrode to a rapid thermal processing (RTP) or furnace anneal step; depositing a dielectric layer on the annealed bottom electrode; depositing a top electrode on the dielectric layer using a plasma-free CVD (chemical vapor deposition) or ALD (atomic layer deposition) process; and patterning the top electrode of each MIM capacitor.

    摘要翻译： 公开了一种用于在MIM（金属 - 绝缘体 - 金属）电容器的制造中形成电极的新颖方法。 该方法通过在电介质层上的顶部电极沉积期间防止等离子体对电介质层的损伤，以及通过减少或防止介电层和电极或电极之间的界面层的形成来改善MIM电容器性能， 在MIM电容器的制造中。 该方法通常包括在衬底中图案化冠状电容器开口; 在每个冠状开口中沉积底部电极; 对底部电极进行快速热处理（RTP）或炉退火步骤; 在退火的底部电极上沉​​积介电层; 使用无等离子体CVD（化学气相沉积）或ALD（原子层沉积）工艺在电介质层上沉积顶部电极; 并对每个MIM电容器的顶部电极进行构图。

    Method and apparatus of holding a device
    44.
    发明授权
    Method and apparatus of holding a device 有权
    握持装置的方法和装置

    公开(公告)号：US08851133B2

    公开(公告)日：2014-10-07

    申请号：US12414861

    申请日：2009-03-31

    申请人： Martin Liu ,  Chung-Yi Yu ,  Che Ying Hsu ,  Yeur-Luen Tu ,  Da-Hsiang Chou ,  Chia-Shiung Tsai

    发明人： Martin Liu ,  Chung-Yi Yu ,  Che Ying Hsu ,  Yeur-Luen Tu ,  Da-Hsiang Chou ,  Chia-Shiung Tsai

    IPC分类号： C23C16/50 ,  C23C16/00 ,  C23F1/00 ,  H01L21/306 ,  H01L21/683

    CPC分类号： H01L21/6838 ,  H01L21/304

    摘要： Provided is an apparatus and a method of holding a device. The apparatus includes a wafer chuck having first and second holes that extend therethrough, and a pressure control structure that can independently and selectively vary a fluid pressure in each of the first and second holes between pressures above and below an ambient pressure. The method includes providing a wafer chuck having first and second holes that extend therethrough, and independently and selectively varying a fluid pressure in each of the first and second holes between pressures above and below an ambient pressure.

    摘要翻译： 提供了一种保持装置的装置和方法。 该装置包括具有穿过其延伸的第一和第二孔的晶片卡盘，以及压力控制结构，其能够在高于和低于环境压力的压力之间独立地和选择性地改变在第一和第二孔中的每一个中的流体压力。 该方法包括提供具有延伸穿过其中的第一和第二孔的晶片卡盘，并且在高于和低于环境压力的压力之间独立地和选择性地改变在每个第一和第二孔中的流体压力。

    Junction leakage reduction through implantation
    46.
    发明授权
    Junction leakage reduction through implantation 有权
    通过植入减少结漏电

    公开(公告)号：US08629013B2

    公开(公告)日：2014-01-14

    申请号：US13273463

    申请日：2011-10-14

    申请人： Chun-Feng Nieh ,  Chung-Yi Yu ,  Hung-Ta Lin

    发明人： Chun-Feng Nieh ,  Chung-Yi Yu ,  Hung-Ta Lin

    IPC分类号： H01L21/338

    CPC分类号： H01L29/66522 ,  H01L21/2654 ,  H01L29/267

    摘要： Provided is a method of fabricating a semiconductor device. The method includes forming a first III-V family layer over a substrate. The first III-V family layer includes a surface having a first surface morphology. The method includes performing an ion implantation process to the first III-V family layer through the surface. The ion implantation process changes the first surface morphology into a second surface morphology. After the ion implantation process is performed, the method includes forming a second III-V family layer over the first III-V family layer. The second III-V family layer has a material composition different from that of the first III-V family layer.

    摘要翻译： 提供一种制造半导体器件的方法。 该方法包括在衬底上形成第一III-V族层。 第一III-V族层包括具有第一表面形态的表面。 该方法包括通过表面对第一III-V族层执行离子注入工艺。 离子注入工艺将第一表面形态变为第二表面形态。 在执行离子注入工艺之后，该方法包括在第一III-V族层上形成第二III-V族层。 第二III-V族层具有不同于第一III-V族层的材料组成。

    TECHNIQUE FOR SMOOTHING AN INTERFACE BETWEEN LAYERS OF A SEMICONDUCTOR DEVICE
    47.
    发明申请
    TECHNIQUE FOR SMOOTHING AN INTERFACE BETWEEN LAYERS OF A SEMICONDUCTOR DEVICE 有权
    用于平滑半导体器件层之间的界面的技术

    公开(公告)号：US20130075837A1

    公开(公告)日：2013-03-28

    申请号：US13240714

    申请日：2011-09-22

    申请人： Chih-Ming Chen ,  Cheng-Yuan Tsai ,  Chung-Yi Yu ,  Kai-Wen Cheng ,  Kuo-Ming Wu

    发明人： Chih-Ming Chen ,  Cheng-Yuan Tsai ,  Chung-Yi Yu ,  Kai-Wen Cheng ,  Kuo-Ming Wu

    IPC分类号： H01L29/82 ,  H01L21/8246

    CPC分类号： H01L27/228 ,  H01L43/08 ,  H01L43/12

    摘要： The present disclosure provides a semiconductor memory device. The device includes a pinning layer having an anti-ferromagnetic material and disposed over a first electrode; a pinned layer disposed over the pinning layer; a composite layer disposed over the pinned layer, the composite layer having a magnetic material randomly distributed in a non-magnetic material; a barrier layer disposed on the composite layer; a free layer disposed over the barrier layer; and a second electrode disposed over the free layer.

    摘要翻译： 本公开提供一种半导体存储器件。 该装置包括具有反铁磁材料并设置在第一电极上的钉扎层; 设置在钉扎层上方的钉扎层; 复合层，其设置在所述被钉扎层上方，所述复合层具有随机分布在非磁性材料中的磁性材料; 设置在所述复合层上的阻挡层; 设置在阻挡层上的自由层; 以及设置在所述自由层上方的第二电极。

    Method for reducing leakage current in a semiconductor device
    50.
    发明申请
    Method for reducing leakage current in a semiconductor device 有权
    减少半导体器件漏电流的方法

    公开(公告)号：US20060278959A1

    公开(公告)日：2006-12-14

    申请号：US11149575

    申请日：2005-06-10

    申请人： Tsung-Hsun Huang ,  Kuo-Yin Lin ,  Chung-Yi Yu ,  Chih-Ta Wu ,  Chia-Shiung Tsai

    发明人： Tsung-Hsun Huang ,  Kuo-Yin Lin ,  Chung-Yi Yu ,  Chih-Ta Wu ,  Chia-Shiung Tsai

    IPC分类号： H01L23/58 ,  H01L21/38

    CPC分类号： H01L21/76829 ,  H01L21/3003 ,  H01L21/3105 ,  H01L21/3143 ,  H01L21/76828

    摘要： A method for reducing leakage current in a semiconductor structure is disclosed. One or more dielectric layers are formed on a semiconductor substrate, on which at least one device is constructed. A hydrogen-containing layer is formed over the dielectric layers. A silicon nitride passivation layer covers the dielectric layers and the hydrogen-containing layer. The hydrogen atoms of the hydrogen-containing layer are introduced into the dielectric layers without being blocked by the silicon nitride layer, thereby reducing leakage current therein.

    摘要翻译： 公开了一种用于减小半导体结构中的漏电流的方法。 一个或多个电介质层形成在半导体衬底上，其上构造有至少一个器件。 在电介质层上形成含氢层。 氮化硅钝化层覆盖电介质层和含氢层。 含氢层的氢原子被引入到电介质层中而不被氮化硅层阻挡，从而减少其中的漏电流。