-
41.发明申请公开(公告)号：US20120081873A1
公开(公告)日：2012-04-05
申请号：US12895251
申请日：2010-09-30
CPC分类号： H05K3/4623 , H05K1/0216 , H05K1/141 , H05K3/368 , H05K2201/10189 , Y10T29/49126 , Y10T29/49162 , Y10T29/53004
摘要： Some embodiments of the inventive subject matter are directed to a first circuit board configured to include an electronic component. The electronic component includes a plurality of leads. The first circuit board includes first wires configured to connect to a first portion of the plurality of leads. The second circuit board is affixed to the first circuit board. The second circuit board includes second wires. The second circuit board is smaller in size than the first circuit board. A plurality of electrical connectors extend through a thickness of the first circuit board and are configured to connect a second portion of the plurality of leads to the second wires.
摘要翻译： 本发明的一些实施例涉及被配置为包括电子部件的第一电路板。 电子部件包括多个引线。 第一电路板包括被配置为连接到多个引线的第一部分的第一布线。 第二电路板固定在第一电路板上。 第二电路板包括第二导线。 第二个电路板的尺寸比第一个电路板小。 多个电连接器延伸穿过第一电路板的厚度，并且被配置为将多个引线的第二部分连接到第二导线。
-
42.发明授权Physical interface macros (PHYS) supporting heterogeneous electrical properties 失效物理接口宏（PHYS）支持异质电气特性公开(公告)号：US08051228B2
公开(公告)日：2011-11-01
申请号：US12270576
申请日：2008-11-13
CPC分类号： G06F13/4022 , G06F13/4072 , G06F2213/0026 , G06F2213/0028 , Y02D10/14 , Y02D10/151
摘要： An integrated processor design includes physical interface macros supporting heterogeneous electrical properties. The processor design comprises a plurality of processing cores and a plurality of physical interfaces to connect to a memory interface, a peripheral component interconnect express (PCI Express or PCIe) interface for input/output, an Ethernet interface for network communication, and/or a serial attached SCSI (SAS) interface for storage.
摘要翻译： 集成处理器设计包括支持异质电气特性的物理接口宏。 处理器设计包括多个处理核心和多个物理接口以连接到存储器接口，用于输入/输出的外围组件互连快速（PCI Express或PCIe）接口，用于网络通信的以太网接口和/或 串行连接SCSI（SAS）接口进行存储。
-
43.发明申请公开(公告)号：US20100220536A1
公开(公告)日：2010-09-02
申请号：US12394804
申请日：2009-02-27
申请人： Paul W. Coteus , Daniel M. Dreps , Kevin C. Gower , Hillery C. Hunter , Charles A. Kilmer , Kyu-hyoun Kim , Kenneth L. Wright
发明人： Paul W. Coteus , Daniel M. Dreps , Kevin C. Gower , Hillery C. Hunter , Charles A. Kilmer , Kyu-hyoun Kim , Kenneth L. Wright
CPC分类号： G11C7/22 , G06F13/1689 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1066 , G11C7/222 , G11C8/12 , Y02D10/14
摘要： A memory device including a memory array storing data, a variable delay controller, a passive variable delay circuit and an output driver. The variable delay controller periodically receives delay commands from a first source external to the memory device during operation of the memory device, and outputs delay instruction bits responsive to the received delay commands. The passive variable delay circuit receives a clock from a second source external to the memory device, receives the delay instruction bits from the variable delay controller, generates a delayed clock having a time relation to the received clock as determined by the delay instruction bits, and outputting the delayed clock. The output driver receives the data from the memory array and the delayed clock, and outputs the data at a time responsive to the delayed clock.
摘要翻译： 一种包括存储数据的存储器阵列，可变延迟控制器，无源可变延迟电路和输出驱动器的存储器件。 可变延迟控制器在存储器件的操作期间周期性地从存储器件外部的第一源接收延迟命令，并且响应于接收的延迟命令而输出延迟指令位。 无源可变延迟电路从存储器件外部的第二源接收时钟，从可变延迟控制器接收延迟指令位，产生与由延迟指令位确定的接收时钟具有时间关系的延迟时钟，以及 输出延迟时钟。 输出驱动器从存储器阵列和延迟时钟接收数据，并且响应于延迟的时钟一次输出数据。
-
44.发明申请Method and Apparatus for Supporting Multiple High Bandwidth I/O Controllers on a Single Chip 有权在单芯片上支持多个高带宽I / O控制器的方法和装置公开(公告)号：US20100122011A1
公开(公告)日：2010-05-13
申请号：US12270569
申请日：2008-11-13
IPC分类号： G06F13/00
CPC分类号： G06F13/385
摘要： An integrated processor design includes physical interface macros supporting heterogeneous electrical properties. The processor design comprises a plurality of processing cores and a plurality of physical interfaces to connect to a memory interface, a peripheral component interconnect express (PCI Express or PCIe) interface for input/output, an Ethernet interface for network communication, and/or a serial attached SCSI (SAS) interface for storage. Each physical interface may be programmatically connected to a selected interface controller, such as a memory controller, a PCI Express controller, or an Ethernet controller, for example. A plurality of such controllers may be connected to a switch within the processor design, with the switch also being connected to each physical interface macro. Thus, the physical interface macros may be programmatically connected to a subset of the plurality of controllers.
摘要翻译： 集成处理器设计包括支持异质电气特性的物理接口宏。 处理器设计包括多个处理核心和多个物理接口以连接到存储器接口，用于输入/输出的外围组件互连快速（PCI Express或PCIe）接口，用于网络通信的以太网接口和/或 串行连接SCSI（SAS）接口进行存储。 每个物理接口可以以编程方式连接到例如存储器控制器，PCI Express控制器或以太网控制器等所选择的接口控制器。 多个这样的控制器可以连接到处理器设计中的开关，开关也连接到每个物理接口宏。 因此，物理接口宏可以以编程方式连接到多个控制器的子集。
-
公开(公告)号：US20080285697A1
公开(公告)日：2008-11-20
申请号：US11749409
申请日：2007-05-16
申请人： Kyu-hyoun Kim , Paul W. Coteus , Daniel M. Dreps
发明人： Kyu-hyoun Kim , Paul W. Coteus , Daniel M. Dreps
IPC分类号： H03D3/24
CPC分类号： H03K5/151 , H03K5/13 , H03K2005/00052 , H03K2005/00234
摘要： A system for providing open-loop quadrature clock generation. The system is implemented by a ring oscillator structure that includes input inverters for receiving an input clock, forward direction loop inverters, backward direction loop inverters, one or more outputs, and cross-coupled latches connected between any two opposite nodes.
摘要翻译： 一种用于提供开环正交时钟生成的系统。 该系统由环形振荡器结构实现，该环形振荡器结构包括用于接收输入时钟的输入反相器，正向环路逆变器，反向环路逆变器，一个或多个输出以及连接在任何两个相对节点之间的交叉耦合的锁存器。
-
公开(公告)号：US07447831B2
公开(公告)日：2008-11-04
申请号：US11383989
申请日：2006-05-18
IPC分类号： G06F13/14
CPC分类号： G06F13/1684 , G06F13/1673 , G06F13/1678 , Y02D10/14
摘要： Memory systems are disclosed that include a memory controller and an outbound link with the memory controller connected to the outbound link. The outbound link typically includes a number of conductive pathways that conduct memory signals from the memory controller to memory buffer devices in a first memory layer; and at least two memory buffer devices in a first memory layer. Each memory buffer device in the first memory layer typically is connected to the outbound link to receive memory signals from the memory controller.
摘要翻译： 公开了包括存储器控制器和与存储器控制器连接到出站链路的出站链路的存储器系统。 出站链路通常包括将存储器信号从存储器控制器传送到第一存储器层中的存储器缓冲器件的多个导电路径; 以及在第一存储器层中的至少两个存储缓冲器件。 第一存储器层中的每个存储器缓冲器件通常连接到出站链路以从存储器控制器接收存储器信号。
-
公开(公告)号：US20080189455A1
公开(公告)日：2008-08-07
申请号：US11670491
申请日：2007-02-02
IPC分类号： G06F13/42
CPC分类号： G06F13/1694
摘要： Multimodal memory controllers are disclosed that include: a transmitter having a first input signal line, a second input signal line, a first output signal line, a second output signal line, a first single-ended driver, a second single-ended driver, a differential transmitter, and a mode control signal line, the mode control signal line having asserted upon it a mode control signal, the transmitter configured to operate the output signal lines using the single-ended drivers at a first voltage when the mode control signal is a first value and to operate the output signal lines using the differential transmitter at a second voltage when the mode control signal is a second value, and the transmitter configured to protect the differential transmitter from the first voltage when the mode control signal is the first value.
摘要翻译： 公开了多模式存储器控制器，其包括：具有第一输入信号线，第二输入信号线，第一输出信号线，第二输出信号线，第一单端驱动器，第二单端驱动器， 差分发射器和模式控制信号线，模式控制信号线已经向模式控制信号断言，所述发射机被配置为当模式控制信号为模拟控制信号时以第一电压使用单端驱动器来操作输出信号线 并且当所述模式控制信号是第二值时，使用所述差分发射机在所述第二电压下操作所述输出信号线，并且所述发射机被配置为当所述模式控制信号是所述第一值时保护所述差分发射机不受所述第一电压的影响。
-
48.发明授权Signal history controlled slew-rate transmission method and bus interface transmitter 失效信号历史控制压摆率传输方式和总线接口发射机公开(公告)号：US07352211B1
公开(公告)日：2008-04-01
申请号：US11466122
申请日：2006-08-22
IPC分类号： H03K19/0175 , H03B5/22
CPC分类号： H04L25/0286 , H04L25/0272
摘要： A signal history controlled slew-rate transmission method and bus interface transmitter provide an improved channel equalization mechanism having low complexity. A variable slew-rate feed-forward pre-emphasis circuit changes the slew rate of the applied pre-emphasis in conformity with the history of the transmitted signal. The pre-emphasis circuit may be implemented by a pair of current sources supplying the output of the transmitter, and having differing current values. The current sources are controlled such that upon a signal value change, a high slew rate is provided and when the signal value does not change for two consecutive signal periods, the slew rate is reduced. A current source having a controlled magnitude may be employed to provide a slew rate that changes over time and is continuously reduced until another transmission value change occurs.
摘要翻译： 信号历史控制的转换速率传输方法和总线接口发射机提供了一种具有低复杂度的改进的信道均衡机制。 可变转换速率前馈预加重电路根据发送信号的历史改变所施加的预加重的转换速率。 预加重电路可以由提供发射机的输出并具有不同电流值的一对电流源来实现。 控制电流源，使得在信号值变化时，提供高压摆率，并且当两个连续信号周期的信号值不变时，转换速率降低。 可以使用具有受控幅度的电流源来提供随时间变化的压摆率，并且持续地减小，直到发生另一个传输值变化。
-
公开(公告)号：US5039952A
公开(公告)日：1991-08-13
申请号：US512304
申请日：1990-04-20
申请人： Daniel M. Dreps , Raymond P. Rizzo
发明人： Daniel M. Dreps , Raymond P. Rizzo
CPC分类号： H03G3/3084 , H03G1/0023
摘要： An amplifier circuit comprises first and second gain cells connected in cascade. Each of the gain cells comprises first and second common emitter differential transistors, a current source coupled to the emitters of the transistors, a first plurality of forward biased, series diodes connected between a power supply terminal and a base of the first transistor, and a second plurality of forward biased, series diodes connected between the power supply terminal and a base of the second transistor. A collector of the first transistor of the first gain cell is connected to the base of the first transistor of the second gain cell, and a collector of the second transistor of a first gain cell is connected to the base of the second transistor of the second gain cell. Because of the low inherent resistance of the biasing diodes, the operating speed of the amplifier is large, and the current amplification can be large without exceeding the power supply voltage. The current source limits the gain for high level signals without causing saturation of the transistors and therefore, does not comprise operating speed. The gain of each cell equals the numbers of diodes connected to the base of the transistor until the level of the current source.
-
公开(公告)号：US20130077724A1
公开(公告)日：2013-03-28
申请号：US13242053
申请日：2011-09-23
CPC分类号： H04L7/0037 , H03L7/0814 , H03L7/085 , H03L7/089
摘要： An embodiment of the invention comprises a digital phase detector with substantially zero phase offset. The digital phase detector receives a clock signal and a reference clock signal and provides a phase indicator signal to identify whether the clock signal leads or lags the reference clock signal. An embodiment of the invention comprises a method that adds substantially zero phase offset in processing an input clock signal and a delayed clock signal to generate a control signal. The control signal is processed in a variable delay line to generate the delayed clock signal. In an embodiment, a first processor comprises a delay locked loop having a digital phase detector, the digital phase detector comprising a first differential sense amplifier cross-coupled to a second differential sense amplifier, the digital phase detector receiving a clock signal and generating one or more delayed clock signals, a control signal, and a gated data signal.
摘要翻译： 本发明的实施例包括具有基本上零相位偏移的数字相位检测器。 数字相位检测器接收时钟信号和参考时钟信号，并提供相位指示符信号以识别时钟信号是引脚还是滞后参考时钟信号。 本发明的实施例包括在处理输入时钟信号和延迟的时钟信号中增加基本上零相位偏移以产生控制信号的方法。 在可变延迟线中处理控制信号以产生延迟的时钟信号。 在一个实施例中，第一处理器包括具有数字相位检测器的延迟锁定环路，数字相位检测器包括交叉耦合到第二差分读出放大器的第一差分读出放大器，数字相位检测器接收时钟信号并产生一个或 更延迟的时钟信号，控制信号和门控数据信号。
-
-
-
-
-
-
-
-
-
搜索结果
90 条记录 (耗时 0.069 秒)
