公开(公告)号：US5789859A

公开(公告)日：1998-08-04

申请号：US755589

申请日：1996-11-25

Applicant: Charles M. Watkins ,  David A. Cathey

Inventor： Charles M. Watkins ,  David A. Cathey

IPC: H01J7/18 ,  H01J9/38 ,  H01J29/94 ,  H01J17/24

CPC classification number: H01J9/38 ,  H01J29/94 ,  H01J7/186 ,  H01J2209/012 ,  H01J2209/385 ,  H01J2329/00

Abstract: The present invention provides an FED with a getter material deposited and activated on the substrates of the faceplate and the baseplate of the FED. In one embodiment of the invention, a large FED includes a faceplate, a baseplate, and an unactivated non-evaporable getter material. The faceplate has a transparent substrate with an inner surface, and a cathodoluminescent material disposed on a portion of the inner surface. The baseplate has a base substrate with a first surface and an emitter array formed on the first surface. The baseplate and the faceplate are coupled together to form a sealed vacuum space in which the inner surface and the first surface are juxtaposed to one another in a spaced-apart relationship across a vacuum gap. The unactivated non-evaporating getter material is deposited directly on the inner surface and/or the first surface. The unactivated non-evaporating getter material may alternatively be deposited on a thin film of bonding material that is disposed on the inner surface and/or the first surface.

公开(公告)号：US5695661A

公开(公告)日：1997-12-09

申请号：US480846

申请日：1995-06-07

Applicant: Robert T. Rasmussen ,  Surjit S. Chadha ,  David A. Cathey

Inventor： Robert T. Rasmussen ,  Surjit S. Chadha ,  David A. Cathey

IPC: H01L21/311 ,  H01L21/3213 ,  H01L21/00

CPC classification number: H01L21/31111 ,  H01L21/02071 ,  Y10S148/051 ,  Y10T428/24802

Abstract: The present invention is directed to a novel etching process for a semiconductor material which inhibits corrosion of metal comprised of pretreating the material, preferably with a surfactant, and then exposing the material to a mixture comprising salt, a buffered oxide etch, and optionally a surfactant.

Abstract translation: 本发明涉及一种用于半导体材料的新型蚀刻工艺，其抑制金属腐蚀，包括预处理材料，优选用表面活性剂，然后将材料暴露于包含盐，缓冲氧化物蚀刻和任选的表面活性剂 。

公开(公告)号：US5496762A

公开(公告)日：1996-03-05

申请号：US253049

申请日：1994-06-02

Applicant: Gurtej S. Sandhu ,  Trung T. Doan ,  David A. Cathey

Inventor： Gurtej S. Sandhu ,  Trung T. Doan ,  David A. Cathey

IPC: H01L21/02 ,  H01L21/8244 ,  H01L27/11 ,  H01L21/70

CPC classification number: H01L28/24 ,  H01L27/11 ,  H01L27/1112 ,  Y10S148/117 ,  Y10S148/136

Abstract: This invention is a process for making resistor structures having high stability and reliability characteristics. Process parameters are easily modifiable to adjust the resistivity of the structures. A layer of titanium nitride, which may contain certain impurities such as carbon, is deposited via chemical vapor deposition by pyrolization of an organometallic precursor compound of the formula Ti(NR.sub.2).sub.4 either alone or in the presence of either a nitrogen source (e.g. ammonia or nitrogen gas) or an activated species (which may include a halogen, NH.sub.3, or hydrogen radicals, or combinations thereof). The TiN film is then oxidized to create a structure that demonstrates highly stable, highly reliable resistive characteristics, with bulk resistivity values in giga ohm range. In a preferred embodiment of the invention, a predominantly amorphous titanium carbonitride film is deposited on an insulative substrate in a chemical vapor deposition chamber. A layer of titanium is then deposited on top of the titanium carbonitride film. The titanium layer is then patterned with photoresist. The exposed titanium is then etched with a reagent that is selective for titanium over titanium carbonitride (HF, for example, has better than 10:1 selectivity) so that the etch essentially stops when the titanium carbonitride film is exposed. The exposed titanium carbonitride film is then oxidized to achieve the desired resistivity.

Abstract translation: 本发明是制造具有高稳定性和可靠性特性的电阻器结构的方法。 工艺参数易于修改以调整结构的电阻率。 可以通过化学气相沉积通过单独或在氮源（例如氨）的存在下热分解式Ti（NR 2）4的有机金属前体化合物来沉积可能含有某些杂质如碳的氮化钛层 或氮气）或活化物质（其可以包括卤素，NH 3或氢基团，或其组合）。 然后将TiN膜氧化，形成表现出高度稳定，高度可靠的电阻特性的结构，体电阻率为千兆欧姆范围。 在本发明的优选实施方案中，主要是无定形的碳氮化钛膜沉积在化学气相沉积室中的绝缘衬底上。 然后将钛层沉积在碳氮化钛膜的顶部。 然后用光致抗蚀剂对钛层进行图案化。 然后用暴露的钛蚀刻钛对碳氮化钛（HF，例如优于10：1选择性）选择性的试剂，使得当碳氮化钛膜暴露时，蚀刻基本上停止。 然后将暴露的碳氮化钛膜氧化以获得所需的电阻率。

公开(公告)号：US5372901A

公开(公告)日：1994-12-13

申请号：US927210

申请日：1992-08-05

Applicant: J. Brett Rolfson ,  David A. Cathey

Inventor： J. Brett Rolfson ,  David A. Cathey

IPC: G03F1/00 ,  G03F1/26 ,  G03F7/20 ,  G03F9/00

CPC classification number: G03F1/26 ,  G03F7/70575

Abstract: A removable bandpass filter layer (22), which is preferably part of a pattern transfer tool (10), improves the resolution of a semiconductor wafer aligner that uses a relatively broad bandwidth radiation source. A narrower bandwidth filter layer provides more complete destructive interference of undesirable diffraction patterns when it is used with a phase-shift pattern transfer tool and removes radiation of longer wavelengths to improve resolution when it is used with a nonphase-shift pattern transfer tool. Using a removable bandpass filter layer, rather than permanently installing a narrow bandpass filter in the aligner, does not affect the speed of patterning layers that do not require the enhanced resolution. The same aligner can thus be used for either high resolution or high throughput without substantial modification to the aligner.

Abstract translation: 优选为图案转印工具（10）的一部分的可拆卸带通滤光层（22）提高了使用相对宽的带宽辐射源的半导体晶片对准器的分辨率。 较窄的带宽滤波器层当与相移图案转移工具一起使用时，提供更为完整的不希望的衍射图形的相消干涉，并且当与非相移图案转印工具一起使用时，可以去除较长波长的辐射以提高分辨率。 使用可拆卸的带通滤光层，而不是在对准器中永久性安装窄带通滤光片，不会影响不需要增强分辨率的图案层的速度。 因此，相同的对准器可以用于高分辨率或高通量而不对对准器进行实质修改。

公开(公告)号：US5358599A

公开(公告)日：1994-10-25

申请号：US84394

申请日：1993-06-29

Applicant: David A. Cathey ,  J. Brett Rolfson

Inventor： David A. Cathey ,  J. Brett Rolfson

IPC: H01L21/30 ,  H01L21/02 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L21/306 ,  B44C1/22

CPC classification number: H01L28/40 ,  H01L21/0274 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/32139 ,  Y10S438/948

Abstract: The subject process relates to the etching of a semiconductor device having a re-entrant profile area which causes residual positive photoresist material to remain therewithin after formation of an etch mask of the positive photoresist material. A negative photoresist etch mask is formed on a major surface of the outer conductive film structural layer. The etch mask comprises a plurality of photoresist lines arranged in a predetermined pattern which defines a plurality of spaces therebetween, which in turn expose a plurality of areas of the major surface of the semiconductor device. Substantially all of the negative photosensitive material located within the re-entrant profile area is removed during the etch mask formation process. The exposed areas of the major surface of the outer structural layer can then be etched to form the requisite etch pattern with a chemical etchant system without regard to interference by unwanted residual photoresist material.

Abstract translation: 本发明涉及一种半导体器件的蚀刻，该半导体器件具有在形成正型光致抗蚀剂材料的蚀刻掩模之后残留的正性光致抗蚀剂材料保留在其中的重新设计的轮廓区域。 在外导电膜结构层的主表面上形成负光致抗蚀剂蚀刻掩模。 蚀刻掩模包括以预定图案布置的多个光致抗蚀剂线，其限定了它们之间的多个间隔，其又暴露半导体器件的主表面的多个区域。 在蚀刻掩模形成工艺期间，基本上所有位于重入轮廓区域内的负感光材料都被去除。 然后可以用化学蚀刻剂系统蚀刻外部结构层的主表面的暴露区域以形成必要的蚀刻图案，而不考虑不想要的残留光致抗蚀剂材料的干扰。

公开(公告)号：US5329207A

公开(公告)日：1994-07-12

申请号：US883629

申请日：1992-05-13

Applicant: David A. Cathey ,  J. Brett Rolfson ,  Tyler A. Lowrey ,  Trung T. Doan

Inventor： David A. Cathey ,  J. Brett Rolfson ,  Tyler A. Lowrey ,  Trung T. Doan

IPC: H01J1/30 ,  H01J1/304 ,  H01J9/02 ,  H01J29/04 ,  H01J31/12

CPC classification number: H01J1/3042 ,  H01J9/025 ,  H01J2201/30407

Abstract: A baseplate for a flat panel display comprising relatively thick semiconductor substrate, wherein the semiconductor substrate is a macro-grain polycrystalline substrate, which is amorphized by ion implantation or reformed by recrystallization, to obscure the grain boundaries, thereafter redundant circuitry may be fabricated thereon to further enhance product yield.

Abstract translation: 一种用于平板显示器的底板，包括相对厚的半导体衬底，其中半导体衬底是通过离子注入而非晶化或通过重结晶重新形成的宏晶多晶衬底，以掩盖晶界，此后可制造冗余电路， 进一步提高产品产量。

公开(公告)号：US5314578A

公开(公告)日：1994-05-24

申请号：US904463

申请日：1992-06-25

Applicant: David A. Cathey

Inventor： David A. Cathey

IPC: H01L21/311 ,  H01L21/00

CPC classification number: H01L21/31116 ,  Y10S438/97

Abstract: A carbon-containing, chemical etchant protective patterned layer is formed on a multi-layer substrate including a silicon dioxide layer formed on an underlying silicon or metal silicide layer by providing a predetermined pattern defining a plurality of openings in the carbon-containing, chemical etchant protective patterned layer. Next, the plurality of exposed areas of the major surface of the silicon dioxide structural layer are selectively etched with a substantially carbon-free chemical etchant system. These materials form a polyhalocarbon material in the presence of a carbon-containing material. Thus, since the chemical etchant protective patterned layer is carbon-containing, a localized polyhalocarbon deposition can be affected, at high selectivity conditions, by adding the carbon-free chemical etchant system in the presence of the protective patterned layer. More specifically, the hydrogen-containing material reacts with the carbon-free, halogen-containing material and the carbon-containing, chemical etchant protective patterned layer to selectively form in situ, at the point of interaction thereof, a polyhalocarbon protective coating layer on the silicon dioxide structural layer.

Abstract translation: 通过在含碳化学蚀刻剂中提供限定多个开口的预定图案，在包含形成在下面的硅或金属硅化物层上的二氧化硅层的多层基底上形成含碳化学蚀刻剂保护性图案层 保护图案层。 接下来，用基本上不含碳的化学蚀刻剂系统选择性地蚀刻二氧化硅结构层的主表面的多个暴露区域。 这些材料在含碳材料的存在下形成多卤碳材料。 因此，由于化学蚀刻剂保护性图案层是含碳的，因此在高选择性条件下，通过在存在保护性图案化层的情况下添加无碳化学蚀刻剂体系，可以影响局部多卤碳沉积。 更具体地说，含氢材料与无碳，含卤素的材料和含碳化学蚀刻剂保护性图案层反应，在其相互作用点上选择性地形成在其上的多卤素保护涂层 二氧化硅结构层。

公开(公告)号：US5281500A

公开(公告)日：1994-01-25

申请号：US754893

申请日：1991-09-04

Applicant: David A. Cathey ,  Brett Rolfson

Inventor： David A. Cathey ,  Brett Rolfson

IPC: G03F1/30 ,  H01L21/027 ,  G03F9/00

CPC classification number: G03F1/30

Abstract: A method of preventing null formation is performed on a phase shifted photomask including a clear quartz substrate, dark chrome feature features, and alternating clear phase shifters raised from the substrate. The phase shifter features are terminated in a transmissive, optically clear edge. To prevent null formation and consequent formation of stringers on the surface of the integrated circuit, the substantially vertical edge of the optically clear end of the phase shifter is tapered. The slope at any point along the tapered edge between the photomask substrate and the phase shifter is set to an angle, typically less than forty-five degrees, shallow enough that the point spread function does not produce an image. The point spread function of the imaging system spreads out the null, which is therefore not printed into the photoresist layer on the integrated circuit. The tapered edge of the phase shifter is created by either discrete or continuous etching methods. Both methods create the phase shifter and tapered edges simultaneously and are compatible with photomasks having either additive or subtractive type phase shifters.

Abstract translation: 对包括透明石英基板，黑铬特征特征的相移光掩模以及从基板凸起的交替的透明移相器执行防止空白形成的方法。 移相器的特征端接在透射光学透明的边缘。 为了防止在集成电路的表面上的空隙形成和随之形成桁条，移相器的光学透明端的基本上垂直的边缘是锥形的。 沿着光掩模基板和移相器之间的锥形边缘的任何点处的斜率被设定为通常小于四十五度的角度，足以使点扩散函数不产生图像。 成像系统的点扩散功能扩展为零，因此不会印刷到集成电路上的光致抗蚀剂层中。 移相器的锥形边缘通过离散或连续蚀刻方法产生。 两种方法同时产生移相器和锥形边缘，并且与具有加法或减法型移相器的光掩模兼容。

公开(公告)号：US5240871A

公开(公告)日：1993-08-31

申请号：US755985

申请日：1991-09-06

Applicant: Trung T. Doan ,  David A. Cathey

Inventor： Trung T. Doan ,  David A. Cathey

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L28/88

Abstract: A dynamic random access memory (DRAM) cell having a corrugated storage contact capacitor for enhancing capacitance. A noncritical alignment is effected between the substrate contact area and the lower capacitor plate by using an etch stop layer to protect wordlines, field-effect transistors (FETs), and field oxide regions during the patterning and etching of storage capacitor regions. The corrugated storage contact capacitor is fabricated by depositing alternating layers of dielectric materials having either substantially different etch rates or wet etch selectivity one toward the other. The layers are isotropically etched and a cavity having corrugated sidewalls is provided. A doped poly layer is deposited to function as the storage-node capacitor plate. The deposition of a dielectric layer is followed by an insitu-doped poly layer deposited to form the upper capacitor plate. The capacitor thus formed is typified as having the storage-node capacitor plate self-aligned to the contact area of the substrate.

Abstract translation: 一种具有用于增强电容的瓦楞存储接触电容器的动态随机存取存储器（DRAM）单元。 在存储电容器区域的图案化和蚀刻期间，通过使用蚀刻停止层来保护字线，场效应晶体管（FET）和场氧化物区域，在衬底接触区域和下电容器板之间实现非临界对准。 波纹存储接触电容器通过将具有基本上不同的蚀刻速率或湿蚀刻选择性的交替层的介电材料沉积到另一个来制造。 各层被各向同性地蚀刻并且提供具有波纹侧壁的空腔。 沉积掺杂多晶硅层作为存储节点电容器板。 介电层的沉积之后是沉积以形成上电容器板的原位掺杂多晶硅层。 由此形成的电容器的特征在于具有与衬底的接触区域自对准的存储节点电容器板。

公开(公告)号：US5082524A

公开(公告)日：1992-01-21

申请号：US559959

申请日：1990-07-30

Applicant: David A. Cathey

Inventor： David A. Cathey

IPC: C23F4/00 ,  H01L21/321 ,  H01L21/3213

CPC classification number: H01L21/32105 ,  C23F4/00 ,  H01L21/32136

Abstract: An enhanced halogenated plasma for ion-assisted plasma etches to which silicon tetrabromide has been added to retard erosion, flowing and reticulation of photoresist, particularly during an etch of an aluminum or tungsten metal layer. The added resistance to erosion, flowing and reticulation is greater than that achieved through the addition of silicon tetrachloride to the same plasma. It is postulated that a silicon-containing layer is deposited on horizontal and vertical surfaces of photoresist at a faster rate than that possible for silicon tetrachloride. As with silicon tetrachloride, resist loss still occurs, but at a much reduced rate, with loss on the upper surfaces of the photoresist segments (these surfaces being perpendicular to the RF field of the reactor) occurring at a higher rate than loss on vertical surfaces (these surfaces being parallel to the RF field of the reactor).

Abstract translation: 用于离子辅助等离子体蚀刻的增强的卤化等离子体，其中已加入四溴化硅以延缓光刻胶的侵蚀，流动和网状化，特别是在蚀刻铝或钨金属层期间。 对侵蚀，流动和网状结构的增加的抵抗力大于通过向同一等离子体中加入四氯化硅所达到的抵抗力。 假设含硅层以比四氯化硅可能的速度更快的速率沉积在光致抗蚀剂的水平和垂直表面上。 与四氯化硅一样，仍然发生抗蚀剂损失，但是以大大降低的速率，在光致抗蚀剂段的上表面（这些表面垂直于反应器的RF场）的损失以比在垂直表面上的损失更高的速率发生 （这些表面平行于反应器的RF场）。