公开(公告)号：US20050161769A1

公开(公告)日：2005-07-28

申请号：US10707905

申请日：2004-01-23

申请人： Douglas Coolbaugh ,  Stephen Furkay ,  Jeffrey Johnson ,  Robert Rassel ,  David Sheridan

发明人： Douglas Coolbaugh ,  Stephen Furkay ,  Jeffrey Johnson ,  Robert Rassel ,  David Sheridan

IPC分类号： H01L29/93 ,  H01L29/94

CPC分类号： H01L29/93 ,  H01L29/94

摘要： A method and device providing a HA junction varactor which may be fabricated with a reduced variation in C-V tuning curve from one varactor to the next. The process produces a varactor with an active region formed substantially by doping an Si substrate with various dopants at various energy levels. Accordingly, unit-to-unit device variation is reduced because etching, growing, and deposition processes to make the active portion of the varactor are reduced or eliminated. The resulting HA junction has a more uniform thickness, and a more uniform doping profile.

摘要翻译： 提供HA结变容二极管的方法和装置，其可以以从一个变容二极管到下一个变容二极管的C-V调谐曲线的变化减小来制造。 该方法产生可变电抗器，其中有源区基本上通过以各种能级掺杂各种掺杂剂的Si衬底而形成。 因此，由于蚀刻，生长和沉积工艺以使变容二极管的活性部分减少或消除，因此减小了单元到单元的装置变化。 所得到的HA结具有更均匀的厚度和更均匀的掺杂分布。

公开(公告)号：US20050070102A1

公开(公告)日：2005-03-31

申请号：US10605439

申请日：2003-09-30

申请人： Douglas Coolbaugh ,  Heidi Greer ,  Robert Rassel

发明人： Douglas Coolbaugh ,  Heidi Greer ,  Robert Rassel

IPC分类号： H01L20060101 ,  H01L21/02 ,  H01L21/302 ,  H01L21/461 ,  H01L27/08

CPC分类号： H01L27/0738 ,  H01L27/0802 ,  H01L28/20

摘要： A process is disclosed for fabricating precision polysilicon resistors which more precisely control the tolerance of the sheet resistivity of the produced polysilicon resistors. The process generally includes performing an emitter/FET activation rapid thermal anneal (RTA) on a wafer having partially formed polysilicon resistors, followed by steps of depositing a protective dielectric layer on the polysilicon, implanting a dopant through the protective dielectric layer into the polysilicon to define the resistance of the polysilicon resistors, and forming a silicide.

摘要翻译： 公开了一种制造精密多晶硅电阻器的方法，其更精确地控制所产生的多晶硅电阻器的薄层电阻率的公差。 该方法通常包括在具有部分形成的多晶硅电阻器的晶片上执行发射极/ FET激活快速热退火（RTA），随后是在多晶硅上沉积保护性介电层的步骤，将掺杂剂通过保护电介质层注入到多晶硅中 限定多晶硅电阻器的电阻，并形成硅化物。

公开(公告)号：US20080099787A1

公开(公告)日：2008-05-01

申请号：US11873696

申请日：2007-10-17

申请人： Douglas Coolbaugh ,  Alvin Joseph ,  Seong-dong Kim ,  Louis Lanzerotti ,  Xuefeng Liu ,  Robert Rassel

发明人： Douglas Coolbaugh ,  Alvin Joseph ,  Seong-dong Kim ,  Louis Lanzerotti ,  Xuefeng Liu ,  Robert Rassel

IPC分类号： H01L27/06

CPC分类号： H01L27/0814 ,  H01L27/0664 ,  H01L27/0823 ,  H01L29/0821 ,  H01L29/7371 ,  H01L29/868

摘要： A structure comprises a single wafer with a first subcollector formed in a first region having a first thickness and a second subcollector formed in a second region having a second thickness, different from the first thickness. A method is also contemplated which includes providing a substrate including a first layer and forming a first doped region in the first layer. The method further includes forming a second layer on the first layer and forming a second doped region in the second layer. The second doped region is formed at a different depth than the first doped region. The method also includes forming a first reachthrough in the first layer and forming a second reachthrough in second layer to link the first reachthrough to the surface.

摘要翻译： 一种结构包括具有形成在具有第一厚度的第一区域中的第一子集电极的单晶片和形成在具有不同于第一厚度的第二厚度的第二区域中的第二子集电极。 还可以设想一种方法，其包括提供包括第一层并在第一层中形成第一掺杂区的衬底。 该方法还包括在第一层上形成第二层并在第二层中形成第二掺杂区域。 第二掺杂区形成在与第一掺杂区不同的深度。 该方法还包括在第一层中形成第一通道并在第二层中形成第二通道以将第一通道连接到表面。

公开(公告)号：US20080067623A1

公开(公告)日：2008-03-20

申请号：US11944839

申请日：2007-11-26

申请人： Douglas Coolbaugh ,  Jeffrey Johnson ,  Xuefeng Liu ,  Bradley Orner ,  Robert Rassel ,  David Sheridan

发明人： Douglas Coolbaugh ,  Jeffrey Johnson ,  Xuefeng Liu ,  Bradley Orner ,  Robert Rassel ,  David Sheridan

IPC分类号： H01L29/872

CPC分类号： H01L29/872 ,  H01L29/0657 ,  H01L29/417 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/861 ,  H01L29/868

摘要： A structure and method of fabricating lateral diodes. The diodes include Schottky diodes and PIN diodes. The method of fabrication includes forming one or more doped regions and more trenches in a silicon substrate and forming metal silicides on the sidewalls of the trenches. The fabrication of lateral diodes may be integrated with the fabrication of field effect, bipolar and SiGe bipolar transistors.

摘要翻译： 制造横向二极管的结构和方法。 二极管包括肖特基二极管和PIN二极管。 制造方法包括在硅衬底中形成一个或多个掺杂区域和更多沟槽，并在沟槽的侧壁上形成金属硅化物。 横向二极管的制造可以与场效应，双极和SiGe双极晶体管的制造集成。

公开(公告)号：US20060166454A1

公开(公告)日：2006-07-27

申请号：US10905940

申请日：2005-01-27

申请人： Douglas Coolbaugh ,  John Florkey ,  Robert Rassel

发明人： Douglas Coolbaugh ,  John Florkey ,  Robert Rassel

IPC分类号： H01L21/20

CPC分类号： H01L21/26513 ,  H01L27/0802 ,  H01L28/20

摘要： Various methods of fabricating a high precision, silicon-containing resistor in which the resistor is formed as a discrete device integrated in complementary metal oxide semiconductor (CMOS) processing utilizing low temperature silicidation are provided. In some embodiments, the Si-containing layer is implanted with a high dose of ions prior to activation. The activation can be performed by the deposition of a protective dielectric layer, or a separate activation anneal. In another embodiment, a highly doped in-situ Si-containing layer is used thus eliminating the need for implanting into the Si-containing layer.

摘要翻译： 提供制造高精度含硅电阻器的各种方法，其中电阻器形成为集成在利用低温硅化物的互补金属氧化物半导体（CMOS）处理中的分立器件）。 在一些实施方案中，在活化之前，用高剂量的离子注入含Si层。 激活可以通过沉积保护性介电层或单独的激活退火来进行。 在另一个实施方案中，使用高掺杂的原位含Si层，因此不需要植入含Si层。

公开(公告)号：US20060046418A1

公开(公告)日：2006-03-02

申请号：US10711130

申请日：2004-08-26

申请人： Douglas Coolbaugh ,  Heidi Greer ,  Robert Rassel

发明人： Douglas Coolbaugh ,  Heidi Greer ,  Robert Rassel

IPC分类号： H01L21/20

CPC分类号： H01L21/2652 ,  H01C17/26 ,  H01C17/265 ,  H01L28/20

摘要： A method of fabricating a resistor in which the resistance value of the resistor is measured and adjusted after silicidation is provided. The method of the present invention begins with first providing at least one resistor, e.g., polysilicon, having a resistance value on a surface of a semiconductor substrate. The at least one resistor has been subjected to a silicidation process. Next, the resistance value of the at least one resistor is measured to determine the actual resistance of the resistor after silicidation. After the measuring step, the resistance of the resistor is adjusted to achieve a desired resistance value. The adjusting may include a post silicidation rapid thermal anneal and/or a post silicidation ion implantation and a low temperature rapid thermal anneal step.

摘要翻译： 提供了在硅化后测量和调整电阻器的电阻值的电阻器的制造方法。 本发明的方法首先开始在半导体衬底的表面上提供具有电阻值的至少一个电阻器，例如多晶硅。 至少一个电阻器已进行硅化处理。 接下来，测量至少一个电阻器的电阻值，以确定硅化后电阻器的实际电阻。 在测量步骤之后，调整电阻器的电阻以获得所需的电阻值。 调整可以包括后硅化快速热退火和/或后硅化离子注入和低温快速热退火步骤。

公开(公告)号：US20070275534A1

公开(公告)日：2007-11-29

申请号：US11839106

申请日：2007-08-15

申请人： Douglas Coolbaugh ,  Louis Lanzerotti ,  Bradley Orner ,  Jay Rascoe ,  David Sheridan ,  Stephen St. Onge

发明人： Douglas Coolbaugh ,  Louis Lanzerotti ,  Bradley Orner ,  Jay Rascoe ,  David Sheridan ,  Stephen St. Onge

IPC分类号： H01L21/331

CPC分类号： H01L21/8222 ,  H01L21/266 ,  H01L27/0825 ,  H01L29/0821 ,  H01L29/36

摘要： Methods are disclosed for forming a varied impurity profile for a collector using scattered ions while simultaneously forming a subcollector. In one embodiment, the invention includes: providing a substrate; forming a mask layer on the substrate including a first opening having a first dimension; and substantially simultaneously forming through the first opening a first impurity region at a first depth in the substrate (subcollector) and a second impurity region at a second depth different than the first depth in the substrate. The breakdown voltage of a device can be controlled by the size of the first dimension, i.e., the distance of first opening to an active region of the device. Numerous different sized openings can be used to provide devices with different breakdown voltages using a single mask and single implant. A semiconductor device is also disclosed.

摘要翻译： 公开了用于使用散射离子形成收集器的不同杂质分布的同时形成子集电极的方法。 在一个实施例中，本发明包括：提供衬底; 在所述基板上形成掩模层，所述掩模层包括具有第一尺寸的第一开口; 并且基本上同时地通过第一开口形成在衬底（子集电极）中的第一深度处的第一杂质区域和与衬底中的第一深度不同的第二深度的第二杂质区域。 装置的击穿电压可以通过第一尺寸的尺寸，即第一开口到装置的有源区域的距离来控制。 可以使用许多不同尺寸的开口来使用单个掩模和单个植入物来提供具有不同击穿电压的装置。 还公开了一种半导体器件。

公开(公告)号：US20050093053A1

公开(公告)日：2005-05-05

申请号：US11001140

申请日：2004-12-02

申请人： Arne Ballantine ,  Douglas Coolbaugh ,  Jeffrey Gilbert ,  Joseph Greco ,  Glenn Miller

发明人： Arne Ballantine ,  Douglas Coolbaugh ,  Jeffrey Gilbert ,  Joseph Greco ,  Glenn Miller

IPC分类号： H01L29/73 ,  H01L21/314 ,  H01L21/318 ,  H01L21/328 ,  H01L21/331 ,  H01L29/08 ,  H01L31/11

CPC分类号： H01L29/66272 ,  H01L21/3144 ,  H01L21/3185 ,  H01L29/0804 ,  H01L29/0895

摘要： A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.

公开(公告)号：US20050054171A1

公开(公告)日：2005-03-10

申请号：US10953378

申请日：2004-09-29

申请人： Jack Chu ,  Douglas Coolbaugh ,  James Dunn ,  David Greenberg ,  David Harame ,  Basanth Jagannathan ,  Robb Johnson ,  Louis Lanzerotti ,  Kathryn Schonenberg ,  Ryan Wuthrich

发明人： Jack Chu ,  Douglas Coolbaugh ,  James Dunn ,  David Greenberg ,  David Harame ,  Basanth Jagannathan ,  Robb Johnson ,  Louis Lanzerotti ,  Kathryn Schonenberg ,  Ryan Wuthrich

IPC分类号： H01L21/331 ,  H01L29/737 ,  H01L21/8222

CPC分类号： H01L29/66242 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/7378

摘要： A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

摘要翻译： 提供了在发射极和集电极区域之间基本上不存在位错缺陷的SiGe双极晶体管及其形成方法。 SiGe双极晶体管包括第一导电类型的集电极区域; 形成在所述集电区域的一部分上的SiGe基区; 以及形成在所述基极区域的一部分上的所述第一导电类型的发射极区域，其中所述集电极区域和所述基极区域在其中连续地包括碳。 SiGe基区进一步掺硼。

公开(公告)号：US20060270203A1

公开(公告)日：2006-11-30

申请号：US10908884

申请日：2005-05-31

申请人： Douglas Coolbaugh ,  Louis Lanzerotti ,  Bradley Orner ,  Jay Rascoe ,  David Sheridan ,  Stephen St. Onge

发明人： Douglas Coolbaugh ,  Louis Lanzerotti ,  Bradley Orner ,  Jay Rascoe ,  David Sheridan ,  Stephen St. Onge

IPC分类号： H01L21/425

CPC分类号： H01L21/8222 ,  H01L21/266 ,  H01L27/0825 ,  H01L29/0821 ,  H01L29/36

摘要： Methods are disclosed for forming a varied impurity profile for a collector using scattered ions while simultaneously forming a subcollector. In one embodiment, the invention includes: providing a substrate; forming a mask layer on the substrate including a first opening having a first dimension; and substantially simultaneously forming through the first opening a first impurity region at a first depth in the substrate (subcollector) and a second impurity region at a second depth different than the first depth in the substrate. The breakdown voltage of a device can be controlled by the size of the first dimension, i.e., the distance of first opening to an active region of the device. Numerous different sized openings can be used to provide devices with different breakdown voltages using a single mask and single implant. A semiconductor device is also disclosed.

摘要翻译： 公开了用于使用散射离子形成收集器的不同杂质分布的同时形成子集电极的方法。 在一个实施例中，本发明包括：提供衬底; 在所述基板上形成掩模层，所述掩模层包括具有第一尺寸的第一开口; 并且基本上同时地通过第一开口形成在衬底（子集电极）中的第一深度处的第一杂质区域和与衬底中的第一深度不同的第二深度的第二杂质区域。 装置的击穿电压可以通过第一尺寸的尺寸，即第一开口到装置的有源区域的距离来控制。 可以使用许多不同尺寸的开口来使用单个掩模和单个植入物来提供具有不同击穿电压的装置。 还公开了一种半导体器件。