公开(公告)号：US08790935B1

公开(公告)日：2014-07-29

申请号：US13801419

申请日：2013-03-13

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Nagel ,  Sarin Deshpande ,  Moazzern Hossain ,  Sanjeev Aggarwal

IPC: H01L21/00 ,  G11C11/00

CPC classification number: H01L43/12 ,  H01L21/76883 ,  H01L21/76898 ,  H01L23/544 ,  H01L27/222 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is provided for forming a first via with an electrically conductive material, for example, copper, that is formed over and coupled to a conductive landing pad of an MRAM array. A sputter step is performed to lower the surface of the first via below that of a surrounding dielectric material. This recess is repeated in subsequent processing steps, providing alignment marks for the formation of a magnetic tunnel junction. The magnetic tunnel junction may be offset from the first via, and a second via being formed above the magnetic tunnel junction and to a conductive layer.

公开(公告)号：US12089418B2

公开(公告)日：2024-09-10

申请号：US18185725

申请日：2023-03-17

Applicant: Everspin Technologies, Inc.

Inventor： Jijun Sun ,  Sanjeev Aggarwal ,  Han-Jong Chia ,  Jon M. Slaughter ,  Renu Whig

IPC: H10B61/00 ,  G11B5/39 ,  G11C11/16 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10B61/00 ,  G11B5/3909 ,  G11C11/1673 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: A magnetoresistive stack/structure and method of manufacturing same comprising wherein the stack/structure includes a seed region, a fixed magnetic region disposed on and in contact with the seed region, a dielectric layer(s) disposed on the fixed magnetic region and a free magnetic region disposed on the dielectric layer(s). In one embodiment, the seed region comprises an alloy including nickel and chromium having (i) a thickness greater than or equal to 40 Angstroms (+/−10%) and less than or equal to 60 Angstroms (+/−10%), and (ii) a material composition or content of chromium within a range of 25-60 atomic percent (+/−10%) or 30-50 atomic percent (+/−10%).

公开(公告)号：US11637235B2

公开(公告)日：2023-04-25

申请号：US16744963

申请日：2020-01-16

Applicant: Everspin Technologies, Inc.

Inventor： Sumio Ikegawa ,  Han Kyu Lee ,  Sanjeev Aggarwal ,  Jijun Sun ,  Syed M. Alam ,  Thomas Andre

IPC: H01L43/04 ,  H01L43/06 ,  H01L43/10 ,  H01L43/14 ,  H01L27/22

Abstract: The present disclosure is drawn to, among other things, a magnetoresistive device and a magnetoresistive memory comprising a plurality of such magnetoresistive devices. In some aspects, a magnetoresistive device may include a magnetically fixed region, a magnetically free region above or below the magnetically fixed region, and an intermediate region positioned between the magnetically fixed region and the magnetically free region, wherein the intermediate region includes a first dielectric material. The magnetoresistive device may also include encapsulation layers formed on opposing side walls of the magnetically free region, wherein the encapsulation layers include the first dielectric material.

公开(公告)号：US11631806B2

公开(公告)日：2023-04-18

申请号：US17317061

申请日：2021-05-11

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph Nagel ,  Kenneth Smith ,  Moazzem Hossain ,  Sanjeev Aggarwal

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/08 ,  H01L21/768 ,  H01L21/285 ,  H01L21/3213 ,  H01L43/02

Abstract: A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via by depositing a second conductive material in the via and directly on the first conductive material in the via; (4) depositing a first electrode material in the via and directly on the second conductive material in the via; (5) polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material in the via and (ii) over the portion of the first conductive material remaining in the via; and (6) forming a magnetoresistive structure over the first electrode material.

公开(公告)号：US11024799B2

公开(公告)日：2021-06-01

申请号：US16360099

申请日：2019-03-21

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Renu Whig ,  Phillip Mather ,  Kenneth Smith ,  Sanjeev Aggarwal ,  Jon Slaughter ,  Nicholas Rizzo

IPC: H01L43/12 ,  B82Y25/00 ,  G01R33/00 ,  G01R33/09 ,  H01L27/22 ,  H01L43/08 ,  H01L43/02

Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.

公开(公告)号：US11005031B2

公开(公告)日：2021-05-11

申请号：US16561418

申请日：2019-09-05

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Nagel ,  Sanjeev Aggarwal

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: A magnetoresistive device may include a first plurality of magnetic tunnel junction (MTJ) bits arranged in a first XY plane, and a second plurality of MTJ bits arranged in a second XY plane that is spaced apart from the first XY plane in a Z direction. And, the MTJ bits of the first plurality of MTJ bits may be spaced apart from the MTJ bits of the second plurality of MTJ bits in the X and Y directions.

公开(公告)号：US10700268B2

公开(公告)日：2020-06-30

申请号：US16108762

申请日：2018-08-22

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph Nagel ,  Sanjeev Aggarwal ,  Sarin A. Deshpande

IPC: H01L43/12 ,  H01L43/08 ,  G11C11/16 ,  H01L43/02 ,  H01L43/10

Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes (a) etching through at least a portion of a thickness of the surface region to create a first set of exposed areas in the form of multiple strips extending in a first direction, and (b) etching through at least a portion of a thickness of the surface region to create a second set of exposed areas in the form of multiple strips extending in a second direction. The first set of exposed areas and the second set of exposed areas may have multiple areas that overlap. The method may also include, (c) after the etching in (a) and (b), etching through at least a portion of the thickness of the magnetoresistive stack through the first set and second set of exposed areas.

公开(公告)号：US10461251B2

公开(公告)日：2019-10-29

申请号：US16107543

申请日：2018-08-21

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev Aggarwal ,  Sarin A. Deshpande ,  Kerry Joseph Nagel

IPC: H01L43/12 ,  H01L27/22

Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes etching through a first portion of the magnetoresistive stack using a first etch process to form one or more sidewalls. At least a portion of the sidewalls includes redeposited material after the etching. The method also includes modifying at least a portion of the redeposited material on the sidewalls, and etching through a second portion of the magnetoresistive stack after the modifying step. The magnetoresistive stack may include a first magnetic region, an intermediate region disposed over the first magnetic region, and a second magnetic region disposed over the intermediate region.

公开(公告)号：US10230046B2

公开(公告)日：2019-03-12

申请号：US15856202

申请日：2017-12-28

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev Aggarwal ,  Kerry Nagel ,  Jason Janesky

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  G11C11/16

Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.

公开(公告)号：US10103197B1

公开(公告)日：2018-10-16

申请号：US15650203

申请日：2017-07-14

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Sanjeev Aggarwal ,  Kerry Joseph Nagel ,  Sarin A. Deshpande

IPC: H01L29/82 ,  H01L43/00 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  H01L43/08

Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.